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geoffm3
February 16th, 2011, 11:54 AM
Does anyone have an example of how to generate the 8th bit for DRAM refresh in a Z80 design? Recall that the Z80 can generate refresh for 7-bits only. I am aware that most DRAMs available today do CAS before RAS... I'm talking for a classical design. I presume you'd use /M1 to determine when the Z80 updates it's internal refresh counter to clock an external 8-bit counter, but perhaps there's a better way.



I have a project that I want to do to reimplement the MIOC from the ADAM, either with PALs or an FPGA. The MIOC is the only custom chip in the ADAM. It has three primary functions:

Provides the 8th bit for DRAM refresh
Bank controller for bank switching RAM into the lower/upper 32kb pages (local or expansion RAM or ROM)
Bus arbitration between the Z80 and the Master 6801 microcontroller (for DMA).

This is the only piece of the ADAM system that isn't documented (other than pinouts). All other parts of the system are off the shelf, and all the firmware is documented.

The idea is later down the road to use the information to either implement the ADAM system in an FPGA or to build a Super ADAM machine with more bankswitching ability and faster clock rates.