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nestor
March 30th, 2011, 02:27 AM
30 pin SIMM DRAM modules are 8 bit data width and they are usually associated is in pairs (16 bit data width) or quartets (32 bit data width). Is it possible to associate 2 or 4 1 MB modules in a way to sum their capacity and maintain the 8 bit width? I have done that with SRAM and a 74LS139, but the SIMMs don't have a /CS line to select one or other...

per
March 30th, 2011, 02:49 AM
The bit-width isn't really the problem as all modules are 8-bit (or 9-bit with pairity) wide. The real problem you are addressing is the address width.

An 286 uses 16-bit data transfers, while the 386+ uses 32-bit data transfers. Because of this, it expects an equal number of address-lines to all modules in a bank. If a 1MB and 4MB modules is mixed in a bank in a 286 system, the bank may appear as 8MB, but the 1MB will be mirrored 3 times within this memory, something you really don't want as this will no doubt lead to corruption of memory.

nestor
March 30th, 2011, 03:09 AM
The idea is, taking your example as a base, to put a 4 MB module and 4 1 MB modules in that 286 bank, so there is really 8 MB. But I don't know if I can associate those 4 modules of 1 MB to behave as a 4 MB module...

per
March 30th, 2011, 03:55 AM
The idea is, taking your example as a base, to put a 4 MB module and 4 1 MB modules in that 286 bank, so there is really 8 MB. But I don't know if I can associate those 4 modules of 1 MB to behave as a 4 MB module...

That should be possible. You will need to buffer all the data-outputs of the modules where you decide which module to "open" based on the two additional address lines. Remember to buffer the input /WE and parity data output too.

Anonymous Coward
March 30th, 2011, 07:10 AM
There are things called "simmverters":

http://www.sourcedata.com/500/000363.html

Personally I'd save yourself the trouble and just buy some more 4meg SIMMs..