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View Full Version : XT-CFv2 rev.B PCB Layout - Request for Comments



pearce_jj
October 13th, 2012, 05:45 AM
Hi, I'd be very grateful for some comments on the layout per the link. A few tweaks from the prototype, I've eliminated connections and components not required, made a few component swaps and changed the pull-ups to operate from 3v3.

PCB front image here. (http://www.lo-tech.co.uk/downloads/temp/v2rb-front.jpg)

Many thanks!

eeguru
October 13th, 2012, 08:22 AM
You are improving young grasshopper. If the back plane is a fairly uncut ground, ship it!

pearce_jj
October 13th, 2012, 01:58 PM
Many thanks!

Compgeke
October 14th, 2012, 02:48 AM
One thing that I would find helpful that would more than likely be expensive would be to have the dip switch settings printed on the board someplace. While I am capable of printing a label, I love when settings are right there.

pearce_jj
October 14th, 2012, 03:45 AM
Thanks - I've been torn on this issue. I've not included them as yet because the programmable logic design means that the switch functions can change. There's no cost implication though.

Chuck(G)
October 14th, 2012, 11:05 AM
I've been using the XT-CFV2 in one of my XTs for awhile now. I like it--small with few issues. I have no problem with using a CF card instead of an IDE drive--it's nice having access to the CF without opening the case. The cool part is that I can insert my CF card into my regular desktop USB adapter (running on Ubuntu) and manipulate files. Make for very easy file transfer.

Crypticalcode0
October 14th, 2012, 12:43 PM
I've only seen two problem area's with copper pour but those can be solved by simply placing a Via there.
And there is something else to near the FPGA but i think that is just a problem with rendering.

I would rate it a 8.5 out of 10.
and that is without seeing the other half, i can see a lot of thought went into this layout.

pearce_jj
October 15th, 2012, 01:02 PM
Thanks very much for the input on this and comments generally!

Crypticalcode0, I'm very interested in your comments, Eagle files are here (http://www.lo-tech.co.uk/downloads/temp/xt-cf-v2b.rar) in case that helps (of course includes both layers too, Alan the back does have quite a bit on it I'm afraid).

eeguru
October 15th, 2012, 01:41 PM
VCC on the JTAG header should be connected to the 3V3 rail. Remove B3 finger and the large 5V loop around the back side (loops are bad anyway fyi).

Both ground pours are pretty cut up yet you don't have any ground vias near any ground pins on any IC. It's going to be difficult to get a wider return on a 2 layers board with that many signals. There are a few routes that could be adjusted to widen places. Coupling the pours near ground pins will help too.

TTL signaling can tolerate quite a lot of ground rise. But no one rain drop causes the flood.

pearce_jj
October 15th, 2012, 09:38 PM
Alan, many thanks for this. The loop was an suggestion over on DP IIRC, but I will make those changes and update the archive later!

pearce_jj
October 16th, 2012, 12:44 PM
I spent some time updating the Eagle files (http://www.lo-tech.co.uk/downloads/temp/xt-cf-v2b.rar), hopefully an improvement but any further comments very gratefully received!