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View Full Version : Hacking Triton II sysboards for 11-bit tag ram



EverythingIBM
April 14th, 2013, 03:23 PM
So-- I have some computers with Triton II chipsets.
They have the smaller tag ram, so they can only cache 64MB. Anything beyond that causes the systems to run quite slowly.

I was wondering if it would be possible to somehow hack the machines with an 11-bit tag ram (so they could utilize all 384MB of the EDO memory WITHOUT getting slow). I'm getting a bit sad seeing my 128 EDO DIMMs go to waste. I bought eight sticks for four dollars years ago.

The alternative route is to use a socket 7 processor with onboard cache, but I'd really prefer if I could keep the pentium. After all, that's what makes it a *Pentium 1* system :p

The systemboards in question are these:
http://az413224.vo.msecnd.net/img/13297/m_13297_27.jpg

Anonymous Coward
April 14th, 2013, 03:33 PM
So by Triton II, do you mean to say you have a 430VX or a 430HX? They are both considered Trition IIs. If you have an HX it might be possible to do something. If you have a VX....not sure. I've never heard of anyone caching more than 64MB on a VX, and intel liked it that way. From what I see in the picture I would say you have an HX chipset based on the package used.

EverythingIBM
April 14th, 2013, 04:20 PM
So by Triton II, do you mean to say you have a 430VX or a 430HX? They are both considered Trition IIs. If you have an HX it might be possible to do something. If you have a VX....not sure. I've never heard of anyone caching more than 64MB on a VX, and intel liked it that way. From what I see in the picture I would say you have an HX chipset based on the package used.

That's correct, it's an HX.

I was just wondering if the tag ram was stored on a certain chip that can be replaced. It would really be nice to use the 384MB of RAM without slowing the system down.

Anonymous Coward
April 14th, 2013, 09:39 PM
Not sure. If the density of the tag RAM is too small for extended caching, chances are a larger one would have a different number of pins. If the extra pads are present, maybe something can be done. If not you are SOL.

Uniballer
April 20th, 2014, 01:19 PM
I have a Shuttle HOT-553 board which uses the Intel 82439HX (430HX) chipset. Online info says it can use a wider tag RAM to increase the cached area, but so far it will only cache the first 64MB of RAM. It has 256KB pipeline burst cache on board, and will run with either an onboard 8Kx8 or 32Kx8 tag RAM. It also has a COAST (cache on a stick) CELP socket. I found a HP 5063-8783 cache module. I could pull the tag RAM from the motherboard and the cache would work with the module instead. I verified that the data lines on the onboard tag RAM were directly paralleled to the ones on the module. So I hacked the module to use tag lines TIO8 - TIO10 instead of some of the others thinking that I could run both the module and onboard tag RAM and get all 11 bits running. But it didn't give me anything extra.

I got a PNY 256KB cache module with Compaq 237716-001 stickers on it because it had pads for an extra tag RAM. I soldered one in and it seems like it should be working, but it doesn't. I have since found out by reading the 82439HX data sheet that you have to enable the extended cache tag bits when the chipset powers up. Any clue of how I do that on a HOT-553? Is there a spot on the motherboard? A code you can set in the presence detect bits on the COAST module? From looking at the original motherboard manual there were cache module differences depending on if it was the first 256KB of cache, the second 256KB of cache, or being used for extended tag. I see some stuff about coding cache size in the COAST PDx bits, but I don't see the tag width there. Is there any way to find this info?

Uniballer
April 22nd, 2014, 01:39 AM
Possibly pertinent information:

Intel COASt specification (any version, but 2.1 seems to be the most relevant to this time period). I have not found any version of this document, but many references to it.

Dealer or service information on Shuttle HOT-553 or similar boards based on the Intel 430HX chipset.

Thanks.

Uniballer
April 24th, 2014, 06:19 PM
I found this on page 2-3 of the Intel 430HX PCIset Design Guide:

• TIO[10]—The state at reset determines the Extended Cacheability Mode (64M or 512M cacheable).
Pull down through 10 kΩ to support 512M mode or pullup with 100K for standard 64M mode.
This signal should also be pulled high when supporting a DRAM cache. If 512M is selected, then
TIO[9:8] must not be pulled up or down.

So I guess that should be pretty easy as long as the TIO10 signal on the COASt socket (pin 88 ) is directly connected to the 82439HX. I'm not sure I can tell as the 82439HX is a BGA, so I'll probably just add the 10K pulldown to the COASt module and see what happens.

Uniballer
April 29th, 2014, 09:40 AM
This strategy does not appear to work with my board, or I messed something up in the implementation.