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modem7
August 17th, 2013, 06:59 PM
On my website, I have updated the description of the IBM 5160's POST to include the checkpoints that the POST generates.

http://www.minuszerodegrees.net/5160/post/5160_post_and_initialisation.htm

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cr1901
August 17th, 2013, 07:12 PM
I presume this is your detailed, researched response to reenigne and I talking about the PPI Port A being an output for a period of time? I still find it a curiosity that the original PC doesn't also have such a POST routine.

Also, this might be semantics, but on this page (http://www.minuszerodegrees.net/5160/post/5160_post_checkpoint_codes.htm), you state:
"But multiple devices are allowed to decode I/O writes, and so a POST card modified to decode port 0x60 will display the checkpoint codes."...

Well, aren't multiple devices also allowed to decode memory writes with the caveat that bad things are likely- and by that I mean near-certain- to happen during a read :P?

modem7
August 17th, 2013, 08:05 PM
I presume this is your detailed, researched response to reenigne and I talking about the PPI Port A being an output for a period of time?
Yes.


Also, this might be semantics, but on this page (http://www.minuszerodegrees.net/5160/post/5160_post_checkpoint_codes.htm), you state:
"But multiple devices are allowed to decode I/O writes, and so a POST card modified to decode port 0x60 will display the checkpoint codes."...
Well, aren't multiple devices also allowed to decode memory writes with the caveat that bad things are likely- and by that I mean near-certain- to happen during a read :P?
Yes, semantics, but I see where you are coming from. I certainly would not want to give 'leaners' the impression that it is always valid for multiple devices to decode the same address/es. I will revise the sentence down to, "A POST card modified to decode port 0x60 will display the checkpoint codes."