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GilesGoat
March 22nd, 2014, 02:33 PM
Hi guys,

to avoid confusion and/or also going off topic in that thread where I was asking about that Microworld Basic I decided to start a new one.

So the story goes more or less like "years ago someone gave me a bag full of weird chips, some where exotic CPUs, to preserve the memory of all this and learn new things from old stuff I embarked on a mission of 'one computer per cpu', this is my SG2650 design".

Must said, when I started all that I did some research but could not find immediately how popular this processor was in Australia nor I did not know very much about other systems, all I found out was the datasheet and some mention of the PIPBUG then I think someway later I found about Arcadia central or such and managed to find some extra documentation and an assembler.

This project been born with the idea of "do something that works that can be still someway useful but with minimal components", it's also been an experiment of mine about finding out "some ways to do things at home", I've done this stuff bits at time during ( little ) free time all with home tools and some .. really OLD tools ..

Anyway I've done my best to document it and put together this PDF ( edited in LATex ) which describes as best ( for now ) the system.

The system is pretty basic, the choice of some chips been literally because "that's what I had at hands" , to save space on board and such ( and to learn more about VHDL ) most of the logic functions been compressed into a single XC9572 CPLD.

If you read the PDF you should be able to make your own mind and use it as a reference/starting point to make your own, this board does not try to emulate or be compatible or such with anything else but it's not "too different" from other stuff I've seen.

The IDE interface, I haven't tested it yet, it's based around Phil's ( Retroleum ) IDE interface, it's nothing special really, it's just a way to write/read 16 bits data from an 8 bits bus by splitting it in two halves and generate a few signals with the correct timings for the IDE protocol.

If you don't care about it you can simply ignore it and make the project even simpler.

Anyway even as it is the board works, you can get to a system where you can do some stuff in it and upload code and run it via XMODEM, I normally use some program like TeraTerm for that and/or my faithful VT220.

This project is for "fun" and "self teaching/learning" there's absolutely NO commercial or such intention whatsoever, it's not even "perfect" or such, it certainly has some defects, it can be optimized, it could have been done better and such but .. "improve it as you like".

In short, here is the PDF, maybe I'll update it a little ( I'll let you know if I do ), enjoy it, make a good use of it, if you want to ask something about maybe do it here on the thread.

Here is the PDF describing the system (http://www.gilesgoat.com/YakLog/SG2650_SBC.pdf).

I hope it will be an interesting and useful thing to read.

If you make some other SG2650 systems please let me know and post something here :)

My next plans for it is :

- test the IDE interface
- have some BASIC working

Enjoy !

GilesGoat
March 23rd, 2014, 01:09 AM
I noted a couple of little errors in the documentation I'll fix them in the next days.

The address space as so far is always as "fist 4K rom/ram, remaining space ram", even if you choose the rom to be 8K you need to change the VHDL code to have 8K of rom instead of ram.

Section 2.3.4 should read TX/RX instead of sense/flag ( victim of cut and paste )

You can find description of the P.R.I.D.E here -> http://www.retroleum.co.uk/electronics-articles/an-8-bit-ide-interface/

The CPLD is XC9536, can be replaced with an XC9572, however as I said the TTL model is hard do find, should be replaced with XL which is 3.3V but TTL input tollerant and add a 3V3 regulator.

The SW used to program the CPLD is the XILINX ISE ( at the time was 10.1 ) you can work it with the latest SW version but beware ISE so far does not work with WIN8, you need WIN7 or an XP machine ( upload cable III - parallel - still works with it and you can build it by yourself ).

The VHDL source should compile and work as it is but I just had to re-format a bit some lines that were too long to fit in the page, not sure if VHDL would complain about me adding some newlines in some parts.

I will have to add a little section about what are the manual modifications, the PCB has a couple of little errors ( some missing tracks ).

The PCB has NO metalized holes, stuff been just soldered both sides, tinning been made with those tinning crystals.

Chuck(G)
March 23rd, 2014, 07:46 AM
Thanks for a look at a nice project!

The 2650 was never very popular, probably due to its limited register set, 8-level stack and 32K limit on memory space. It might have made a decent microcontroller, were it not for the competition. However, the peripherals attracted some attention--the 2651 (and later 2661) were very advanced USART chips with internal baud rate dividers; even better than the Intel 8251A. Lots of those were used and the 2651 persisted long after the 2650 itself.

GilesGoat
March 30th, 2014, 12:53 PM
Still working a bit on it to port that BASIC on .. I found another couple of small bugs :

Those two lines :

CPLDROM equ 0 ; write to this, first 8K = ROM
CPLDRAM equ 8 ; write to this, first 8K = RAM

Should be like this instead :

CPLDROM equ 0 ; write to this, first 8K = ROM
CPLDRAM equ 4 ; write to this, first 8K = RAM

Likewise the documentation about UART mentions A2 in some point but in reality is A0, in fact if you look in the schematics is pin ADR0 that is connected to RS not ADR2.

I am making a small "bootloader" of another kind that allows me to load programs/stuff in memory at address 0 or such.

I'll let you know how it goes.


Basically, the idea is you assemble it with the ORG you want, you load it at 2000H and then the "bootloader" flips the mem and copies it in the right
locations and jumps to it, I came out so far with a thing like this one :


BLOADR: eorz R0
wrte,r0 CPLDRAM ; set location 0000H .. to be RAM
stra,R0 Zero_const
cpsl 05H ; ensure carry is 0

; lodi,R0 lo(bootmsg)
eorz R0
; lodi,RO lo(start)
stra,R0 Start_l
; lodi,R0 hi(bootmsg)
; lodi,R0 hi(start)
addi,R0 20H ; ensure high part is +2000H
stra,R0 Start_h

; lodi,R0 40h
; stra,R0 Dest_h
; lodi,R0 00h
; stra,R0 Dest_l

lodi,R0 hi(start)
stra,R0 Dest_h
lodi,R0 lo(start)
stra,R0 Dest_l

; so far START = 2000H and Dest = where 'start' is

cpsl 05H ; ensure carry is 0
lodi,R0 hi(BLOADR)
addi,R0 20h
stra,R0 Size_h
lodi,R0 lo(BLOADR)
stra,R0 Size_l

; halt

; cpsl 04H ; ensure carry is 0
ppsl 09H ; ensure WC is 1 and C is 1
suba,R0 Start_l ; size_l -= start_l
stra,R0 Size_l
loda,R0 Size_h
suba,R0 Start_h ; size_h -= start_h - CC
stra,R0 Size_h

; cpsl 08H ; ensure WC is 0000H
; halt


; now size has the correct size


cp_lp loda,R0 *Start_h ; R0 = *(Start_h,Start_l)
stra,R0 *Dest_h

cpsl 01H ; ensure carry is 0
lodi,R0 1
addr,R0 Start_l
strr,R0 Start_l
lodr,R0 Zero_const
addr,R0 Start_h
strr,R0 Start_h ; plus carry of course

cpsl 01h
lodi,R0 1
addr,R0 Dest_l
strr,R0 Dest_l
lodr,R0 Zero_const
addr,R0 Dest_h
strr,R0 Dest_h ; plus carry of course

ppsl 01H ; ensure carry is 1
lodr,R0 Size_l
subi,R0 1
strr,R0 Size_l
lodr,R0 Size_h
subr,R0 Zero_const
strr,R0 Size_h ; plus carry of course

iorr,R0 Size_l
bcfr,EQ cp_lp ; go in loop if not zero

cpsl 08H ; ensure WC is 0000H
bcta,UN start ; start the shit
; halt

Start_h db 0
Start_l db 0
Dest_h db 0
Dest_l db 0
Size_h db 0
Size_l db 0
Zero_const db 0


end



Got quite a bit nuts with the story of the carry bit ...