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JackLeather
June 29th, 2014, 03:58 AM
Hello all!

I finally got my hands on a PET 8032 (board #8032080) but it needs attention!

I have primarily used this excellent thread to troubleshoot:
http://www.vintage-computer.com/vcforum/showthread.php?30199-My-first-attempt-at-PET-Repair-Model-4016-Advice-Welcome

I would class myself with beginner to intermediate competency in electronics. I have a multimeter and CRT scope (Hitachi V-423 40Mhz) that I must admit I don't really know how to use/read.

Symptoms: no start up beep and no video.

steps so far (using various threads):
-board has been cleaned.
-voltages appear fine on at the transformer and on all major chips (6502, CRTC, RAM and ROM)
-i have removed 6520's and 6522.
-processor is getting its 1Mhz CLK and gets the RESET signal
-successfully read the 'BIZ CHIP' in my EPROM programmer. more below on the ROMs.

-12" monitor doesn't appear to have any HT but the heater is powering up so that needs fixing at some point.

I am at the point where i think one or all of my ROMs are dead. I have some questions...

ROM/EPROM Questions:

I have a cheap USB EPROM programmer that claims it works with all sorts of EPROMS excluding 2532s of course (but including 2732(A+B)). I constructed an adapter as here:
http://arcadecontrols.com/BBBB/mspacrom.html

I can read the BIZ CHIP EPROM in UD12 fine. When I try the original PET ROMs in UD6-UD10 I only get $FF. Is this expected? Could they all be faulty giving the same results or is it because the adapter wont work with the ROMs?

I have plenty of 27128 16k EPROMs can I adapt to 4k and program with PET bins?

Video/CRTC Questions:

I have a working CRTC chip now (from a BBC micro) it the HD46505SP (the PET had the same), I understand a clone of the Motorola 6845.

Is the initially set-up, performed by UD7, of the CRTC chip responsible for the 20khz\50hz horizontal\vertical frequencies? I am unable to make any sense of the signals from the CRTC pins 39/40.

Here is what i get from J7 on my scope - time/div = .2ms and volts/div = .5
Horizontal - pulse 1 division vertically (.5 volts) and pulses horizontally of about 1 and 1/5th of a div, going negative (back to 0) for about 0.1 of a div. Is this 20khz?
Vertical - Continuously High at 1 div (.5 volts)
Video - Random pulses of at 1 div (.5 volts)

I thought I was getting 20khz horizontal but to be honest I'm not sure how to read the scope properly how do i measure 50hz, can someone assist with reading the above frequencies?

Because the monitor appears to have issues I have constructed the PET video mixer circuit (from below)
http://home.comcast.net/~medasaro/6540rom.com/petvideo.html

Will it function with my CRTC PET as I just read it for the TTL version??

Any help will be much appreciated!

dave_m
July 15th, 2014, 09:36 AM
ROM/EPROM Questions:

I have a cheap USB EPROM programmer that claims it works with all sorts of EPROMS excluding 2532s of course (but including 2732(A+B)). I constructed an adapter as here:
http://arcadecontrols.com/BBBB/mspacrom.html

I can read the BIZ CHIP EPROM in UD12 fine. When I try the original PET ROMs in UD6-UD10 I only get $FF. Is this expected? Could they all be faulty giving the same results or is it because the adapter wont work with the ROMs?



The adapter will not work. Pin 21 of the ROM should be at +5V. You can hook up pin 24 (VCC) of the 2732 to the ROM pin 21, but make sure to insulate the wire so it can not touch anything else.

dave_m
July 15th, 2014, 07:46 PM
Video/CRTC Questions:

Is the initially set-up, performed by UD7, of the CRTC chip responsible for the 20khz\50hz horizontal\vertical frequencies? I am unable to make any sense of the signals from the CRTC pins 39/40.

Here is what i get from J7 on my scope - time/div = .2ms and volts/div = .5
Horizontal - pulse 1 division vertically (.5 volts) and pulses horizontally of about 1 and 1/5th of a div, going negative (back to 0) for about 0.1 of a div. Is this 20khz?
Vertical - Continuously High at 1 div (.5 volts)
Video - Random pulses of at 1 div (.5 volts)



Yes the CRTC init code is in the Editor ROM (UD7) and sets up the 6545 one time right after power up.
I assume you are using a 10X probe as the signals should be at 5V not 0.5V. I can't make much sense out of your description of the waveforms, but assume if you are getting waveforms that the Horizontal Drive is OK. The Vertical Drive is a little hard to see properly as it is a skinny negative pulse every 20 mS. Try to trigger on the negative edge and increase the intensity to see the skinny pulse.

If the signals are OK, and there is no display, then there is something wrong up in the video board. There is an 18VDC regulator output that you will have to check. There is also a 56 ohm resistor that tends to pop.

JackLeather
July 16th, 2014, 09:39 AM
The adapter will not work. Pin 21 of the ROM should be at +5V. You can hook up pin 24 (VCC) of the 2732 to the ROM pin 21, but make sure to insulate the wire so it can not touch anything else.

Many thanks for this tip! I later read this, which worries me;


Reading mask ROMS (take care!)

You might want to use your EPROM programmer to read a mask ROM to see if it's damaged. As mentioned above, unless the mask ROM is pin compatible with an EPROM that the programmer supports you'll need to make an adapter first to switch the mask ROMs pins to those matching the supported EPROM. Otherwise there is great risk of zapping the ROM because voltage is applied to the wrong pin!

This adapter technique can be also used to read or program EPROMS that are not supported by your programmer as I did with these 2532 EPROMS for my Pet 3032.


The original ROMs are mask ROMS, correct?

I'll modify my adapter and try and read them again.


Yes the CRTC init code is in the Editor ROM (UD7) and sets up the 6545 one time right after power up.
I assume you are using a 10X probe as the signals should be at 5V not 0.5V. I can't make much sense out of your description of the waveforms, but assume if you are getting waveforms that the Horizontal Drive is OK. The Vertical Drive is a little hard to see properly as it is a skinny negative pulse every 20 mS. Try to trigger on the negative edge and increase the intensity to see the skinny pulse.

If the signals are OK, and there is no display, then there is something wrong up in the video board. There is an 18VDC regulator output that you will have to check. There is also a 56 ohm resistor that tends to pop.

Yes my probe was set to x10!

I later got hold of cheap digital scope and re-read the 6845s pin 39/40.

+--------------+
GND |1 |||| 40| VSYNC -> ???? [random noise]
/RST |2 39| HSYNC -> 4Khz [1000/ 50 = 20khz : 1000/ *255* = 3.92Khz]
LPSTB |3 38| RA0 [horiz freq = 1000 / ( byte at E72A +1 ) Khz]
MA0 |4 37| RA1

With the help of zimmers site and some hope I think I have deduced that why HSYNC is about 4Khz.
- if the ROMs are dead (or I fried them) and they are writing &FF (see previous post) to the 6845 HSYNC register the frequency would be [1000/ 50 = 20khz : 1000/ *255* = 3.92Khz]

What do you think? good hypothesis?



Because the monitor appears to have issues I have constructed the PET video mixer circuit (from below)
http://home.comcast.net/~medasaro/65.../petvideo.html

Will it function with my CRTC PET as I just read it is for the TTL version??

What do you think about this? Should it work?

dave_m
July 16th, 2014, 01:58 PM
The original ROMs are mask ROMS, correct?

Yes, the are mask ROMs (programmed during fab of chip).



I later got hold of cheap digital scope and re-read the 6845s pin 39/40.

+--------------+
GND |1 |||| 40| VSYNC -> ???? [random noise]
/RST |2 39| HSYNC -> 4Khz [1000/ 50 = 20khz : 1000/ *255* = 3.92Khz]
LPSTB |3 38| RA0 [horiz freq = 1000 / ( byte at E72A +1 ) Khz]
MA0 |4 37| RA1

With the help of zimmers site and some hope I think I have deduced that why HSYNC is about 4Khz.
- if the ROMs are dead (or I fried them) and they are writing &FF (see previous post) to the 6845 HSYNC register the frequency would be [1000/ 50 = 20khz : 1000/ *255* = 3.92Khz]

What do you think? good hypothesis?

No, as the code that writes the data into the 6545 is also in the E000 ROM.

First things first, find out which of your ROMs are bad. Then when they are replaced, everything may be OK. Without a proper HSYNC of 20KHz, the CRT high voltage may not be generated. I assume you do not get a 'chirp' on power up? This may indicate the CPU is not running due to bad ROM and/or RAM. Hang on the to the scope, you may need it for future troubleshooting.
-Dave

dave_m
July 16th, 2014, 02:09 PM
The adapter will not work. Pin 21 of the ROM should be at +5V. You can hook up pin 24 (VCC) of the 2732 to the ROM pin 21, but make sure to insulate the wire so it can not touch anything else.

You could probably just leave pin 21 of the ROM open and it should look like a high input. This would not work to try to read a 2532 EPROM, in that case the pin 21 would have to be held to +5V.

JackLeather
July 18th, 2014, 10:40 AM
Yes, the are mask ROMs (programmed during fab of chip).



No, as the code that writes the data into the 6545 is also in the E000 ROM.

First things first, find out which of your ROMs are bad. Then when they are replaced, everything may be OK. Without a proper HSYNC of 20KHz, the CRT high voltage may not be generated. I assume you do not get a 'chirp' on power up? This may indicate the CPU is not running due to bad ROM and/or RAM. Hang on the to the scope, you may need it for future troubleshooting.
-Dave

Of course you are right, code and initialisation data are both in E000 UD7! Darn it - I thought I was onto something - maybe the default value for the 6854 HSYNC register is 255?

No chirp at start up, unfortunately.


You could probably just leave pin 21 of the ROM open and it should look like a high input. This would not work to try to read a 2532 EPROM, in that case the pin 21 would have to be held to +5V.

I will make the mod and try again this weekend and report back.

Thanks so far!

JackLeather
July 19th, 2014, 07:27 AM
I disconnected pin 21 of the ROM and my programmer keeps complaining that there's a pin/contact issue. Do you know of the location of the ROM pin outs and example of the ROM adapter so I may check my wiring?

dave_m
July 20th, 2014, 08:55 AM
I disconnected pin 21 of the ROM and my programmer keeps complaining that there's a pin/contact issue. Do you know of the location of the ROM pin outs and example of the ROM adapter so I may check my wiring?

For ROM pinouts simply use the 8032 ROM schematic page HERE (http://zimmers.net/anonftp/pub/cbm/schematics/computers/pet/univ2/8032087-04.gif).

All socket pins straight through except: On the top socket for the ROM, make sure pins 18, 20 and 21 are isolated and do NOT make contact with their bottom socket counterparts and then jumper:

Top Bottom
18--21 A11
20--18 CE/
21--24 Vcc (note pin 24 of top socket may be used to connect top socket pin 21 if easier to connect as it is Vcc also)

Take care against inadvertent shorts.

The spec sheet for the 2332 ROM can be viewed HERE (http://generalthomas.com/PET/2332 ROM.pdf). Note that there is a typo in the description where it states that the 2732 EPROM is pin compatible; they mean the 2532.

JackLeather
July 21st, 2014, 11:48 AM
Looks like you were spot on - UD7 and UD8 appear to be bad.

*I downloaded the ROM images from zimmers site and loaded them into my programmer to get the checksum and compare.


Good - UD6 - 901465-22 checksum = CF19H

Bad - UD7 - 901474-04 checksum = F000H
I only managed to read it once
Its this one:
901474-04-3681
Screen editor for BASIC 4, business keyboard, CRTC, 80 columns, 50 Hz. The chip is dated 3681. There are some differences from the other archived copies of from:
http://zimmers.net/anonftp/pub/cbm/firmware/computers/pet/

Bad - UD8 - 901465-21 - checksum bad (should be A425H)
I get different results each time i read it (9EA4H/9E3BH/AAC5H/A37AH)

Good - UD9 - check sum ok
901465-20-5960H

Good - UD10 - check sum ok
901465-23-4168H

I not 100% sure my programmer can write 2732 EPROMs (forget 2532s) - Is there a source of PET ROMs anywhere than anyone knows of?

JackLeather
July 23rd, 2014, 12:05 PM
NOTE: sorry if this is a duplicate but i've waited since Sunday for my last post to appear.

Dave - you were right!

I downloaded the .bin images of the PET ROMS from zimmers site and loaded them into my programmer to get the checksum and then compared with my real ROMs which I had read. Here are the results:



GOOD - UD6 - 901465-22

BAD - UD7 - 901474-04 (The chip is dated 3681)

BAD - UD8 - 901465-21

GOOD - UD9 - 901465-20

GOOD - UD10 - 901465-23



Update: Since Sunday I managed to get hold of one 2732 which I should receive soon. how should I change the adapter to first blow then actually use in the
PET?

Can anyone help me out with obtaining another?

dave_m
July 27th, 2014, 08:22 AM
Update: Since Sunday I managed to get hold of one 2732 which I should receive soon. how should I change the adapter to first blow then actually use in the
PET?

Can anyone help me out with obtaining another?

On the prom programmer you should not need an adapter for the 2732 as they all handle that part.

In the PET, again use a double socket with the top socket having pins 18, 20 and 21 straight out and isolated from the bottom socket. It may be earlier to use the legs of the EPROM.

Then jumper leg 18 to bottom socket pin 20 (CE/)
leg 20 can be grounded or tied to leg 18 (OE/)
Jumper leg 21 to bottom pin 18 (A11)

I have sent a PM with more information.
-Dave

JackLeather
July 27th, 2014, 10:53 AM
PM replied!

MikeS
July 28th, 2014, 09:13 AM
Because the monitor appears to have issues I have constructed the PET video mixer circuit (from below)
http://home.comcast.net/~medasaro/65.../petvideo.html

Will it function with my CRTC PET as I just read it is for the TTL version??
What do you think about this? Should it work?Unfortunately, no, at least not with a 'normal' composite NTSC monitor; you might at least get some scrambled video though. Unlike the 9" non-CRTC models, the scan rates are not compatible; the CRTC can be reprogrammed to work, but of course the PET has to be working.

Where in the world are you, by the way?

JackLeather
July 28th, 2014, 10:35 AM
Unfortunately, no, at least not with a 'normal' composite NTSC monitor; you might at least get some scrambled video though. Unlike the 9" non-CRTC models, the scan rates are not compatible; the CRTC can be reprogrammed to work, but of course the PET has to be working.

Where in the world are you, by the way?

Hi Mike! I'm in the UK - London to be a little more precise.

Do you know of a PET 8032 -> PAL composite mod? I'm not sure if the PET's monitor is working so I could do with some other way to get video out of it.

MikeS
August 5th, 2014, 11:45 AM
Hi Mike! I'm in the UK - London to be a little more precise.

Do you know of a PET 8032 -> PAL composite mod? I'm not sure if the PET's monitor is working so I could do with some other way to get video out of it.I don't think there's much difference between PAL and NTSC when you're talking monochrome; the problem is that the 8032's scan frequencies are substantially higher than either one. An adapter like the one you reference would combine and convert the signal levels to be compatible with a composite monitor but you would have to reprogram the CRTC to make the frequencies compatible, and of course the PET has to be working for that. I think that there are a few monitors capable of the 8032's scan rates but they're few and far between.

Any chance there's anyone in your neighbourhood with a PET with a working 12" screen that you could swap with?

Maybe SteveG can shed a little more light on this?...

dave_m
August 10th, 2014, 06:20 PM
OK, so the E000 & D000 ROMs didn't fix the problem. With the scope, take look at the horizontal drive for a 20 KHz signal. See if the Sync signal on the 6502 CPU is a 25% duty cycle waveform. That will tell if CPU is fetching instructions.

JackLeather
August 11th, 2014, 10:19 AM
OK, so the E000 & D000 ROMs didn't fix the problem. With the scope, take look at the horizontal drive for a 20 KHz signal. See if the Sync signal on the 6502 CPU is a 25% duty cycle waveform. That will tell if CPU is fetching instructions.

Pin 7 (SYNC) of the CPU just shows noise and pin 39 (HSYNC) is as before at 4khz.

dave_m
August 11th, 2014, 05:36 PM
Jack reported no Sync or Address activity (he is new so his posts are delayed). Jack, check for good 1 MHz input to Phase 0. If good clock, then replace CPU. Also check for faulty 40 pin socket
-Dave.

dave_m
August 17th, 2014, 02:47 PM
Jack reported no Sync or Address activity (he is new so his posts are delayed). Jack, check for good 1 MHz input to Phase 0. If good clock, then replace CPU. Also check for faulty 40 pin socket
-Dave.


Jack reported:
"I replaced the CPU socket - no change!


Clocks:
P0 - 1Mhz
P1 - 1Mhz
P2 - *Read below


*I can only read this with my probe set at x10 where it reads 1Mhz.


Address bus lines are all at 3.6v.


Maybe i need to move to replacing the ROM sockets?


What should i see on the SYNC pin? what frequency? I see a spike roughly every 3/4 of a second on my cheap digital scope. maybe i should try it with my CRT scope."

Jack,
Keep using the 10X probe with the voltage range set at about 0.2V per division.

The Sync should go high for one clock cycle (1 microsecond) when the CPU is fetching an instruction. It is low during execution of the instructions. So normally Sync will go high for one cycle and then low for three or more cycles. You should see an aperiodic waveform running at about 250 KHz or slower if the CPU is running. So it doesn't seem like the CPU is running even though it is getting a good clock input. What are the 8 data lines doing? The first step is to get the CPU running properly. We should have activity on many of the address lines (especially the lower ones) and data lines.

Even if the ROMs are outputting bad data the CPU should run although I think if it reads certain illegal instructions it can get struck and Sync will stay low.

JackLeather
August 18th, 2014, 10:56 AM
Jack,
Keep using the 10X probe with the voltage range set at about 0.2V per division.

The Sync should go high for one clock cycle (1 microsecond) when the CPU is fetching an instruction. It is low during execution of the instructions. So normally Sync will go high for one cycle and then low for three or more cycles. You should see an aperiodic waveform running at about 250 KHz or slower if the CPU is running. So it doesn't seem like the CPU is running even though it is getting a good clock input. What are the 8 data lines doing? The first step is to get the CPU running properly. We should have activity on many of the address lines (especially the lower ones) and data lines.

Even if the ROMs are outputting bad data the CPU should run although I think if it reads certain illegal instructions it can get struck and Sync will stay low.

Some progress (thanks Dave) with my scope set 10x, 0.2v and 1us:
- I see 3x 500khz square waves at each power up on SYNC then it goes low. Photo attached.
- I also see a flash of pulses on some data and address bus lines.

The data bus ends up frozen with voltages:

D0 - 0.03
D1 - 0.03
D2 - 2.3
D3 - 0.03
D4 - 0.13
D5 - 2.3
D6 - 2.3
D7 - 2.3

It appears that the CPU is only executing 3 instructions.

19950

dave_m
August 18th, 2014, 04:05 PM
Jack Reports:
Some progress (thanks Dave) with my scope set 10x, 0.2v and 1us:
- I see 3x 500khz square waves at each power up on SYNC then it goes low. Photo attached.
- I also see a flash of pulses on some data and address bus lines.


The data bus ends up frozen with voltages:


D0 - 0.03
D1 - 0.03
D2 - 2.3
D3 - 0.03
D4 - 0.13
D5 - 2.3
D6 - 2.3
D7 - 2.3


It appears that the CPU is only executing 3 instructions.


The 2.3V does not seem to be a proper level. A good high should be above 3.2V. Can you check the $F000 ROM again?

On power-up, the 6502 should fetch the low byte starting address (RESET Vector) from address $FFFC and the high bye address from $FFFD. It then puts the address into the program counter and starts running. The first address to run on an 8032 PET is $FD16. In other words ROM address $FFFC should contain $16 and $FFFD should contain $FD.

It appears the machine is not getting past this stage. I'll have to think about that...

There is a diagnostic program that can be placed in the $F000 ROM socket that will initialize the CRT Controller and run a simple RAM test. You can program it into a 2732 and place in PET with an socket adapter.
-Dave

NOTE to Moderators: Can we take JackLeather off probation so he can post in a timely manner?

JackLeather
August 23rd, 2014, 03:28 AM
Progress, the CPU is running!!!

UD8 - D000 ROM wasn't seated properly :rolleyes:

Now I am seeing SYNC doing as expected and Address and Data line going wild everywhere. :D

However the CRTC chip still isn't outputting 20Khz - HSYNC is still at 4Khz and VSYNC is just noise at pins 39/40.

dave_m
August 23rd, 2014, 05:32 PM
However the CRTC chip still isn't outputting 20Khz - HSYNC is still at 4Khz and VSYNC is just noise at pins 39/40.

That is good news. The problem now could be that either the 6545 CRT Controller (UB-13) is not being initialized by the CPU on power up due to a memory problem on the E000 EPROM or the 6545 is bad. To find out it will be necessary to probe the chip select on UB13 at UB13- pin25 and see if there is a series of negative skinny pulses there on power-up. If so, the 6545 is being addressed but is not functioning. First check the 2716 (UD7) for bent pins and proper seating.
-Dave

JackLeather
August 24th, 2014, 07:27 AM
That is good news. The problem now could be that either the 6545 CRT Controller (UB-13) is not being initialized by the CPU on power up due to a memory problem on the E000 EPROM or the 6545 is bad. To find out it will be necessary to probe the chip select on UB13 at UB13- pin25 and see if there is a series of negative skinny pulses there on power-up. If so, the 6545 is being addressed but is not functioning. First check the 2716 (UD7) for bent pins and proper seating.
-Dave

UB13 is a 6845 (HD46505) - I pulled it from a working BBC Micro and have just tried it again in the BBC and its still OK. Pin 25 goes high (4.2v) and stays there i dont see any negative pulses at power up. I have double checked UD7 with a multimeter and all pins are making contact with the socket.

I notice from the schematic UB13 CS is driven by I/O, X8XX and B7. What exactly is X8XX for? Under what circumstance is UB13 CS pulsed?

I read through some of the ROM disassembly start-up code and it appears that the VIA and PIA are set up before the CRTC - is there anyway i can confirm their state?

dave_m
August 24th, 2014, 09:31 AM
UB13 is a 6845 (HD46505) - I pulled it from a working BBC Micro and have just tried it again in the BBC and its still OK. Pin 25 goes high (4.2v) and stays there i dont see any negative pulses at power up. I have double checked UD7 with a multimeter and all pins are making contact with the socket.


I notice from the schematic UB13 CS is driven by I/O , X8XX and B7. What exactly is X8XX for? Under what circumstance is UB13 CS pulsed?


I read through some of the ROM disassembly start-up code and it appears that the VIA and PIA are set up before the CRTC - is there anyway i can confirm their state?


The signal I/O BAR is the address decode of the $EXXX space, i.e., it goes low when the address lines are between $E000 and $EFFF. However only addresses above $E8000 are I/O.
The signal X8XX goes high when address bit A11 is high and A10, A9 and A8 are low, i.e. whenever the address includes $800 such as $E800. Used to help specify I/O addresses.
The signal BA7 is buffered address line 7 the final part of decoding the $E880 to $E88F address space of the 6545 CRT Controller. The 6545 is only initialized right after power up. It may be hard to catch the pulses without a logic analyzer or memo scope. You might have to set the screen persistence high and use single trigger. That might be a bit advanced for you right now.

No way to check the VIA and PIA until the PET comes up.

Do you see any negative pulses on the signal "I/O BAR"? I/O may occur more often and will be easier to see. Remember these are skinny 1 microsecond negative pulses. The Tektronix 465 can be set up to see them.

EDIT: Sorry about scope callout. I got mixed up with another thread. Is the scope you are using capable of capturing data after a trigger?

JackLeather
September 6th, 2014, 06:33 AM
I blew your pettest2.bin onto a 2732 and it initialised the CRTC, I see 20khz and 60hz! :D

I want to use the source code to create an EPROM that will program my CRTC to output 50hz (I'm in the UK) so I can then hook up the monitor and see what happens.

The original 60hz code:


F220 .BYTE 31 28 29 0F 20 03 19 1D
.BYTE 00 09 00 00 10 00 00 00
.BYTE 00 00


I think I need (changes highlighted):




F220 .BYTE 31 28 29 0F 27 00 19 20 ;1().'..
.BYTE 00 09 00 00 10 00 00 00 ;........
.BYTE 00 00 ;..



Is this correct?

dave_m
September 7th, 2014, 12:27 AM
Jack,
Any luck with the detecting a pulse on the chip select for the 6545 CRT Controller at power-up?

dave_m
September 7th, 2014, 10:58 AM
I tried the 50hz bin image you created (thank a lot for helping me out!) on a 2732 and it does indeed program the CRTC with 20khz/50hz. I hooked it up to the PET monitor but alas nothing was displayed - would appear i have a dead display as well as everything else :(

I don't given up easily :D

What should I learn from this? looks like the pettest50hz.bin EPROM can address the CRTC but i'm not getting a chirp.

No, pettest does not chirp the PET. Without the UB15 6522, it will not beep anyway.

Does the CRT tube light up? Turn up the brightness. Can you see diagonal retrace or anything?

Anyway we have to find out why your ROMs do not initialize the CRTC. Do you get any pulses on the signal 'I/O'?