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NeXT
April 9th, 2015, 07:17 PM
An AltairClone has zero consideration for adding an S100 bus inside the extremely empty case (http://images.gizmag.com/inline/altair-8800-clone-4.jpg) if one so desired, but nothing says that with a LOT of diodes you could isolate the lamps and swiches and toggle between the onboard emulation and control of a real S100 machine. (or just disable the emulation completely) That being said, I'm not exactly sure how the front panel interfaces with the bus.

Referring to this photo (http://tkc8800.com/images/MITS_Altair8800/Altair8800_card_view.JPG) I can see a number of lines interface with the bus directly and others feed into the CPU card.
Referring to this photo (http://www.vintagecomputer.net/MITS/8800a/MITS_Altair8800a_bare-front-panel.jpg) also indicates the front panel PCB isn't entirely passive.

Also, are there layouts of something like an 8-slot S100 bus somewhere I could use to send off to a board house for etching? I see photos of various people and their own designs but no actual layout files.

tkc8800
April 9th, 2015, 08:20 PM
I swear I've seen the Altair int hat first pic somewhere.

1944GPW
April 9th, 2015, 08:39 PM
You can find a circuit diagram for an S100 front panel in the PDF from here http://www.s100computers.com/Hardware%20Folder/Wameco/FPB/FPB.htm which should show you the logic needed to interface to the bus. This one does use 7-segment LEDs instead of discrete binary LEDs but some TTL decoding ought to be able to handle that.

Steve

Chuck(G)
April 9th, 2015, 10:17 PM
MITS packaged the cheapest white hookup wire that they could find with the kit. As I recall, it's pretty easy to break one of the wires with simple fatigue stress. Add to that the problem of nicking a conductor while stripping.

Then there's the issue of running live AC line traces on the front panel PCB. Let your hand probe around a bit in back of the PCB and you can get a nasty surprise. IMSAI had a much better design, to their credit.

TJ_Mossman
April 11th, 2015, 09:07 AM
MITS packaged the cheapest white hookup wire that they could find with the kit. As I recall, it's pretty easy to break one of the wires with simple fatigue stress. Add to that the problem of nicking a conductor while stripping.

I concur... I've fixed, broke, and fixed again several wires on my Altair no more than an hour ago.

NeXT, you might want to look at the schematics and layout for the original front panel board that can be found here: http://www.classiccmp.org/dunfield/altair/altair6.htm

AFAIK the clone's front panel PCB lines up with the original panel, but the dress panel isn't a drop-in replacement. Still, I've thought about it myself and I'm sure it's do-able.
There's some S-100 backplanes for sale via the N8VEM project, I think the layouts are available too but I've not checked.

NeXT
April 13th, 2015, 08:25 AM
Those schematics were exactly what I was hunting for. Thanks TJ. Those will go a long way towards my plans. Don't worry, I'll be publishing the photographed project when it gets finished. ;)

Novell2NT
October 16th, 2018, 04:59 AM
I am working on what might be a bad logic chip on the front panel of an Altair 8800a.
A6-A11 go high when we first hit Examine.

Do you have any schematics for the front panel?

Please take a look at this video, and let me know if you have any ideas, of what we should be looking for.

https://drive.google.com/open?id=1Zeh6D76Aj0-NZFUOJlosx3T3kXKhML3T


Thank you

deramp5113
October 16th, 2018, 07:56 AM
Looks like IC-B is bad, or if socketed, pull and reinsert the chip a few times to improve pin contact and see if the problem goes away.

Here’s a schematic http://deramp.com/downloads/altair/hardware/altair_8800_computer/Altair%20Schematics.pdf

Mike

Novell2NT
October 16th, 2018, 09:31 AM
Looks like IC-B is bad, or if socketed, pull and reinsert the chip a few times to improve pin contact and see if the problem goes away.

Here’s a schematic http://deramp.com/downloads/altair/hardware/altair_8800_computer/Altair%20Schematics.pdf

Mike

Thanks for getting back to me Mike.

Is IC-B on memory board? We are using a known good memory board.
At this point we are assuming the problem may be a front panel logic issue.

Thank you

deramp5113
October 16th, 2018, 11:50 AM
Take a minute and look at the schematic link I provided previously. In that file you’ll see a schematic for the front panel board. On that schematic you’ll see that IC-B drives switches A6-A11, which are the ones you’re having problems with.

Mike

Novell2NT
October 16th, 2018, 01:21 PM
Take a minute and look at the schematic link I provided previously. In that file you’ll see a schematic for the front panel board. On that schematic you’ll see that IC-B drives switches A6-A11, which are the ones you’re having problems with.

Mike

Thank you for clarifying, we found the IC-B chip you are referring to on the schematic. I will let you know, what we find out.

We will compare it to working machine.

Thank you again !!!

Novell2NT
October 17th, 2018, 02:46 AM
Take a minute and look at the schematic link I provided previously. In that file you’ll see a schematic for the front panel board. On that schematic you’ll see that IC-B drives switches A6-A11, which are the ones you’re having problems with.

Mike

Hey Mike,

Where are you located? I am planning a cross country trip in March, From Washington to Florida, I like to meet other collectors on my way home.
I met some great collectors when I made the same trip from CA back to FLA last year. Do you have a website?

www.theageofgaming.com

Jeff

deramp5113
October 17th, 2018, 04:38 AM
Hey Mike,

Where are you located? I am planning a cross country trip in March, From Washington to Florida, I like to meet other collectors on my way home.
I met some great collectors when I made the same trip from CA back to FLA last year. Do you have a website?

www.theageofgaming.com

Jeff

Jeff,

I’m in the Dallas, TX area. My website for the vintage computing hobby is http://deramp.com

Come on by!

Mike

Novell2NT
October 17th, 2018, 05:38 AM
Jeff,

I’m in the Dallas, TX area. My website for the vintage computing hobby is http://deramp.com

Come on by!

Mike

Nice collection, love it... I would like to get a SOL-20 and a IMSAI, to round out my computer collection.

The trip from Seattle Washington back to Florida in March, unfortunately does not go through Texas this time.
I wanted to check out the NVM up there in Dallas, the last time we went through, but it was getting late, by the
time we got up that way from Austin.

One of these days I will get back up that way, so look for a knock on your door. As I would love to see the vintage
computers that you have restored back to life.

Do you have any suggestions, on testing the floppy drive unit that came with my Altair. I am worried about trying to apply
power to it.

https://drive.google.com/open?id=1197OVi0OuEAg0k7n2Arh3aOdeOli8QS8

deramp5113
October 17th, 2018, 05:57 AM
Based on the pictures, your Altair is configured closer to a Sol-20 than to an Altair. Your Altair has the ”Subsystem B” board set from Processor Technology that makes any S100 computer pretty much the same as a Sol-20. Looks like you’ve got the North Star single density floppy controller as well. My guess is your disks are North Star DOS and/or CP/M 1.4?

The disk images and transfer utilities at the link below can be used to archive the disks you have and to create new disks. I’d like to know what your disk labels say is on your disks and possibly archive them with you before putting them at risk in your drives.

http://deramp.com/downloads/processor_technology/sol-20/software/northstar_sd_controller/

Mike

Novell2NT
October 17th, 2018, 07:21 AM
Based on the pictures, your Altair is configured closer to a Sol-20 than to an Altair. Your Altair has the ”Subsystem B” board set from Processor Technology that makes any S100 computer pretty much the same as a Sol-20. Looks like you’ve got the North Star single density floppy controller as well. My guess is your disks are North Star DOS and/or CP/M 1.4?

The disk images and transfer utilities at the link below can be used to archive the disks you have and to create new disks. IÂ’d like to know what your disk labels say is on your disks and possibly archive them with you before putting them at risk in your drives.

http://deramp.com/downloads/processor_technology/sol-20/software/northstar_sd_controller/

Mike


This is getting funnier by the minute. The guy who I have working on my Altair lives in Austin. He has actually purchased a couple of your drop in floppy controllers, and that is what he is using to
work with on my Altair. I told him, if he gets up that way, that he should stop by and meet you in person.

I have not received the Altair, so I do not know, what disks are included.

I did notice on your website that you do have a Northstar system. I have two NorthStar Advantage 8/16 systems, one that boots up and one that I use for parts. Could not get the floppy drives to work properly.
and of course the keyboard pads were dissolved. So, I created new ones, probably not has good as the originals.
I also have a huge collection of unopened software packages for NorthStar and a bunch of opened binders as well. If you are interested in any of these items, just let me know, and I will work on
mailing them out to you.

Ricky is doing a good job with my Altair, but I do not think he will be able to work with the floppy drive or the old memory boards. So, when he is done, I might ask him to mail it up to you, if you have
the time and are willing to take a look at it.


If you send me your email address, I will send you some pics of the NorthStar systems and software packages that I have here. They are just taking up room in my garage right now. It would be nice
to give them a good home.

Dwight Elvey
October 17th, 2018, 10:33 AM
I was looking at your posted problem. It isn't clear that you understand fully how the front panel works. The address displayed is from the CPU, not the front panel. The way it works is that when you hit Examine, it sequences the instruction C3, Low, High onto the data port of the CPU as a fetched value, by the processor. This is done by pulsing the 7405s onto to the CPU at the right time. The CPU attempts to read this location but put into WAIT by the front panel. C3 is the 8080 jump instruction.
Examine Next put a NOP on the CPU's data ports as the instruction.
The address displayed should be the address lines on the S100 addresses, by the CPU, not the address switches, when something doesn't work right.
It helps to have a digital scope or logic analyzer to see the enabling pulse sequences to the 7405s when doing the Examine. A logic probe with a pulse detect can be used but may not always give you the timing information needed in some cases.
On the 10th sheet you can see the 7405s that are used to force the CPU data port.
I hope this information help you on your debugging.
Dwight

Novell2NT
October 17th, 2018, 11:22 AM
I was looking at your posted problem. It isn't clear that you understand fully how the front panel works. The address displayed is from the CPU, not the front panel. The way it works is that when you hit Examine, it sequences the instruction C3, Low, High onto the data port of the CPU as a fetched value, by the processor. This is done by pulsing the 7405s onto to the CPU at the right time. The CPU attempts to read this location but put into WAIT by the front panel. C3 is the 8080 jump instruction.
Examine Next put a NOP on the CPU's data ports as the instruction.
The address displayed should be the address lines on the S100 addresses, by the CPU, not the address switches, when something doesn't work right.
It helps to have a digital scope or logic analyzer to see the enabling pulse sequences to the 7405s when doing the Examine. A logic probe with a pulse detect can be used but may not always give you the timing information needed in some cases.
On the 10th sheet you can see the 7405s that are used to force the CPU data port.
I hope this information help you on your debugging.
Dwight

Thanks for the information Dwight, we are looking at the IC-B (7405) on the front panel on page 10, because we know the CPU card and memory card are good.
The IC-B 6 inverters (7405) just happen to be connected to SA6-SA11. of the front panel.
If the switches were locked into the up position, and you hit examine, and you do not have the correct signal coming out of all 6 inverters of the IC-B chip, you would get all highs out.

If we were not sure that the CPU card was good or not, I would check the buffer chips. on the CPU board 8T28s The only problem with that, is that A6-A9 are on Buffer driver C and A10-A11 are on buffer drive D. There are two other address lines on buffer C (A12, A15) and buffer driver D has four other lines it handles.

My first thought was to check the address lines as well, but there is not a single chip that handles A6-A11 specifically. The only one that does, is the IC-B (7405) on the front panel.

I believe that Page 10, that you are referring to, is the Front Panel Logic board. and the 7405 that you are referring to, is the IC-B that we are looking at.

I do appreciate how you were able to explain, the steps involved in doing a fetch, to get the address information as well as the data information onto the buss and then get the LEDs to light up.

Thank you

Dwight Elvey
October 17th, 2018, 12:59 PM
Thanks for the information Dwight, we are looking at the IC-B (7405) on the front panel on page 10, because we know the CPU card and memory card are good.
The IC-B 6 inverters (7405) just happen to be connected to SA6-SA11. of the front panel.
If the switches were locked into the up position, and you hit examine, and you do not have the correct signal coming out of all 6 inverters of the IC-B chip, you would get all highs out.

If we were not sure that the CPU card was good or not, I would check the buffer chips. on the CPU board 8T28s The only problem with that, is that A6-A9 are on Buffer driver C and A10-A11 are on buffer drive D. There are two other address lines on buffer C (A12, A15) and buffer driver D has four other lines it handles.

My first thought was to check the address lines as well, but there is not a single chip that handles A6-A11 specifically. The only one that does, is the IC-B (7405) on the front panel.

I believe that Page 10, that you are referring to, is the Front Panel Logic board. and the 7405 that you are referring to, is the IC-B that we are looking at.

I do appreciate how you were able to explain, the steps involved in doing a fetch, to get the address information as well as the data information onto the buss and then get the LEDs to light up.

Thank you

You are most likely right about which chip to replace. It is clearly the only one that can be an issue.
There is another thing that always catches people and that is the DO5 signal coming in( on the previous page ). I had to think about this one for some time. What it is is that the CPU sends out status information. The front panel need to know the difference between an instruction fetch and an address fetch. DO5 bit tells the front panel that.
The reason I go through how it works is because just looking at the schematic, one often doesn't understand the function of the processor. When the front panel seems to fail, it is good to verify that the processor is healthy. If you have another board CPU board it is good to try swapping it to see if the problem goes away.
Another thing that causes problem is that the Data connector cable can be connected backwards. The C3 works OK because even if the bits are swapped end to end it is still C3. The addresses will be mixed up.
Anyway, replace the 7405 and it sounds like you are on your way.

Novell2NT
October 20th, 2018, 05:51 AM
You are most likely right about which chip to replace. It is clearly the only one that can be an issue.
There is another thing that always catches people and that is the DO5 signal coming in( on the previous page ). I had to think about this one for some time. What it is is that the CPU sends out status information. The front panel need to know the difference between an instruction fetch and an address fetch. DO5 bit tells the front panel that.
The reason I go through how it works is because just looking at the schematic, one often doesn't understand the function of the processor. When the front panel seems to fail, it is good to verify that the processor is healthy. If you have another board CPU board it is good to try swapping it to see if the problem goes away.
Another thing that causes problem is that the Data connector cable can be connected backwards. The C3 works OK because even if the bits are swapped end to end it is still C3. The addresses will be mixed up.
Anyway, replace the 7405 and it sounds like you are on your way.

Sorry, I did not receive this message.

I did have a crazy idea of something to check, maybe you can tell me, what would happen, if instead of toggling Examine, which causes A6-A11 to go high,
we toggle "Examine Next" instead of Examine, while all the address lines are at Zero?
In theory, this could show a problem with the Examine switch process.

Dwight Elvey
October 20th, 2018, 06:40 AM
Examine Next only uses the bottom 8 inverters seen in the schematic. The address outputs from the front panel should have no effect. The processor already has the address loaded from reset. It forces a NOP for the CPUs instruction fetch.
Dwight

Novell2NT
October 20th, 2018, 10:35 AM
Examine Next only uses the bottom 8 inverters seen in the schematic. The address outputs from the front panel should have no effect. The processor already has the address loaded from reset. It forces a NOP for the CPUs instruction fetch.
Dwight

Have you ever met Bob Rosenbloom in Santa Cruz? He has the biggest collection, I have ever seen.

https://www.youtube.com/watch?v=2OkTm0vI7As

I met him, last year, when I was driving my wife home from CA.

Dwight Elvey
October 20th, 2018, 11:08 AM
Have you ever met Bob Rosenbloom in Santa Cruz?

Yep, Bob and I are friends. He has been trying to down size. He's had a number of items up for sale on ebay.
He still has the largest collection I've seen outside of some museums.
Dwight

Novell2NT
October 20th, 2018, 11:41 AM
Yep, Bob and I are friends. He has been trying to down size. He's had a number of items up for sale on ebay.
He still has the largest collection I've seen outside of some museums.
Dwight

I am from Florida, so I did not like driving around up in the hills. LOL!!! But it was worth it, I am still in Awe of the awesome collection he has there.
and whenever I have a question, he is always willing to give me the answer.

I met a couple of collectors on the way home from CA. I had a great time. Being a tourist, I had to stop by Steve Jobs old garage and take a pic.

I also met Steve at www.oldcomputers.net he has a nice collection as well, just no big stuff like Bob has.

Now, I was looking at the Examine Next signal, and it looked like it went off in two directions. One of those directions was to the last 8 inverters 4-D's and 4-E's.
The other direction I saw it heading was to the PRDY. Do Is there something I am missing here?

You would think, that it would simply increment the address lines one at a time.

Dwight Elvey
October 20th, 2018, 09:25 PM
You would think, that it would simply increment the address lines one at a time.

You miss what I said. The micro processor is executing the NOP instruction. It is driving the addresses, not the front panel. When you do a examine next, it just executes a NOP. This causes it to sequence to the next address. The S100 bus is isolated from the CPUs data bus so the processor only sees instructions from the front panel until you hit the RUN or SINGLE STEP. The processors address lines drive the bus. The front panel never directly drives the S100 address lines. It only drives the S100 data lines for the DEPOSIT operation, otherwise it displays the S100 adressesed data pointed to by the processors address lines.
The front panel only does two different instructions. NOP and JMP. It uses the JMP instruction to load the address from the front panel switches into the processor. The sequential addressing is just the processor fetching the next NOP instruction.
You recall, I mention the D5 line going to the logic. That is the tricky part. The JMP is actually three fetches. One is the instruction, next is the low byte of the address and last is the high byte of the address. The front panel needs to let the processor execute by itself when fetching the two address bytes but know to stop before fetching the next instruction. It does this by watching the processor status. The D5 bit from the processor just happens to contain the instruction fetch status ( I believe called M1 ). This allows the front panel to stop before the processor sees the next instruction. The front panel can then choose the source of the next instruction, from either the S100 bus or NOP/JMP from the front panel. So, you see the processor is doing the harder work of running the address, the front panel can then be simpler in a sense. When you hit RUN, the front panel doesn't have to tell the processor what address to start at, it just starts at either the reset or at the last address left by the Examine operation.
The D5 is also used by the single step to stop, only, at the fetch of the next instruction, regardless of if it is a 1, 2 or 3 byte instruction.
Dwight

Novell2NT
October 21st, 2018, 04:37 AM
You miss what I said. The micro processor is executing the NOP instruction. It is driving the addresses, not the front panel. When you do a examine next, it just executes a NOP. This causes it to sequence to the next address. The S100 bus is isolated from the CPUs data bus so the processor only sees instructions from the front panel until you hit the RUN or SINGLE STEP. The processors address lines drive the bus. The front panel never directly drives the S100 address lines. It only drives the S100 data lines for the DEPOSIT operation, otherwise it displays the S100 adressesed data pointed to by the processors address lines.
The front panel only does two different instructions. NOP and JMP. It uses the JMP instruction to load the address from the front panel switches into the processor. The sequential addressing is just the processor fetching the next NOP instruction.
You recall, I mention the D5 line going to the logic. That is the tricky part. The JMP is actually three fetches. One is the instruction, next is the low byte of the address and last is the high byte of the address. The front panel needs to let the processor execute by itself when fetching the two address bytes but know to stop before fetching the next instruction. It does this by watching the processor status. The D5 bit from the processor just happens to contain the instruction fetch status ( I believe called M1 ). This allows the front panel to stop before the processor sees the next instruction. The front panel can then choose the source of the next instruction, from either the S100 bus or NOP/JMP from the front panel. So, you see the processor is doing the harder work of running the address, the front panel can then be simpler in a sense. When you hit RUN, the front panel doesn't have to tell the processor what address to start at, it just starts at either the reset or at the last address left by the Examine operation.
The D5 is also used by the single step to stop, only, at the fetch of the next instruction, regardless of if it is a 1, 2 or 3 byte instruction.
Dwight

Hey Dwight,

Do you have a document that goes through this process? I would love to learn more about the basic functions, that make the Altair work. Something like a good hardware/ operation manual or troubleshooting guide.

Novell2NT
October 21st, 2018, 04:44 AM
I think I just found a good document, that goes over the front panel operation pretty well.

http://www.classiccmp.org/dunfield/altair/d/88theory.pdf

Dwight Elvey
October 21st, 2018, 05:40 AM
Do note that it shows the JMP instruction as 303, which is in octal. In hex, that I prefer for bytes, it is C3. Octal has an advantage when looking at 8080 instructions. Note that there are 8 possible source and destinations. Once one learns these, hand assembling and disassembling 8080 code is easier in octal. Dealing with addresses, fetched as bytes is clumsier in octal than in hex. That is why I've found hex more useful. Still, I have a 20 bit machine and since all the operations are a full 20 bits, octal works fine.
In any case, this document is fine but one still has to examine the schematic to see how it all combines together. It doesn't go to deep into things like why D5 is chosen as a signal that controls the operation. It does mention D5 in the RUN/STOP. For this one has to study the 8080 data sheet and timing diagrams.
Dwight

Novell2NT
October 21st, 2018, 01:01 PM
Do note that it shows the JMP instruction as 303, which is in octal. In hex, that I prefer for bytes, it is C3. Octal has an advantage when looking at 8080 instructions. Note that there are 8 possible source and destinations. Once one learns these, hand assembling and disassembling 8080 code is easier in octal. Dealing with addresses, fetched as bytes is clumsier in octal than in hex. That is why I've found hex more useful. Still, I have a 20 bit machine and since all the operations are a full 20 bits, octal works fine.
In any case, this document is fine but one still has to examine the schematic to see how it all combines together. It doesn't go to deep into things like why D5 is chosen as a signal that controls the operation. It does mention D5 in the RUN/STOP. For this one has to study the 8080 data sheet and timing diagrams.
Dwight

OK !!! YEAH !!! I figured out how the 303 gets onto the Data Bus. Like I said the 2 inverter on C and 2 inverters on D that are connected to D2-D5, they do not put a 303 on the data bus.
What they do is pull D2-D5 down (Low).

Leaving D0-D1 and D6-D7 high 11000011

Then the Examine Next puts a NOP on the data bus using 4 inverters on D and 4 inverters on E, pulling all 8 data line down. This simply increments the Program Counter.

I must have read that thing 5 times, till it finally stuck. LOL!!! Better late than never ....

Chuck(G)
October 21st, 2018, 02:00 PM
I thought all of this was covered in the Altair 8800 documentation. I seem to recall that it is, at any rate.

On the topic of front panel workings, somewhere there's a 74L00 used in a wired-OR configuration. You can't use a 7400/74LS00/74S00/74HCT00 in that position because the 'L00 uses a resistive pullup. You can, however, use a 7403 and add a pullup to each output.

Dwight Elvey
October 21st, 2018, 07:18 PM
Yes, Chuck it is covered but it takes a little while to go from ones thinking of how it works to how it actually works.
I was impressed the first time I figured it out. I do understand that the idea of using the processor to do the address work was not new but at the time, I had no other machines for reference.
I one I think is often an issue with the Altair is that if the cable is plugged in with D0 to D7 swapped to D7 to D0, the front panel will seem to work but some addresses come out wrong. I've seen this happen to others at least half a dozen times.
Dwight