View Full Version : New V3 Version of teh S100 bus System monitor Board gone out to users

April 10th, 2015, 04:19 PM
The final "production version" of our V3 SMB came in from China this week. Glad (and relieved to say -- there were 30 boards) that the board checks out OK. The only issue I have found is that the 3 digit bus clock frequency (PHI) is always 1MHz less than expected. i.e. 10 MHz Z80 shows 9.99MHz, a 8MH 8086 shows up as 7.99MHz. The construction notes and details about the board can be found at the bottom of this page:-


Here is the shipping list I worked from:-

Ian McLaughlin 1

Fabio Battaglia 3

Tom Lafleur 1

Brian Marstella 1

David Fry 1

Matthew Turner 3

Neil Breeden 1

Leon Byles 1

J. Alexander Jacocks 1

Jedi Master (Dave) 2

Eric Osman 1

Jack Rubin (will give to you at VCF next week)

Don Caprio (Will give to you when we meet next week)

Todd Goodman 3

Pete Plank 1

Paul Birkel 2

Robert Greenstreet 1

Rick Bromagem 1

Tim Acker 1

Hope I got everybody. Almost all the components of the V1 or V2 boards can be used in this board. This one is just better arranged using the GAL for fast 8 & 16 bit port addressing - a problem with some in the past for master/slave CPU switching.

For payments, send $16/board. Read the stamp cost and PayPal to me WHEN you receive the board. I'm counting on everybody following the "honor system" , I don't have time to track everything. Just shipping these board out took a full day!

Status of things...

Next is the corresponding V3 version of our Dual IDE/CF board. Again a GAL (actually 2) are used for a faster/simpler layout. This time I had 4 production board ordered from China to test first. That way I'm not sweating with a backlog of boards that may have an error! This will be my approach from now on. Also in the works is a "V4" version of our old tried and true 16MB static RAM board, two GAL, no daughter board, SMD RAM 8 or 16MB RAM, with adjustable wait states. "The last S100 bus RAM board you will ever need!".

My main focus, the S100 bus 80486 master/slave CPU board is turning out to be more difficult that anticipated. Now on version 3. I seriously misunderstood how the data is passed into and out of the CPU in 8, 16 or 32 bit wide modes.