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JGardner
August 14th, 2015, 06:22 AM
512 KB RAM, <and> blinkenlights...

Does it get any better? :)

krebizfan
August 14th, 2015, 07:49 AM
What do you do with 512kB RAM on that?

JGardner
August 14th, 2015, 08:35 AM
...What do you do with 512kB RAM on that?

Just about anything you might do with a PDP-8.

Except run up a big electric bill. Easier to move too... :)

krebizfan
August 14th, 2015, 09:18 AM
...What do you do with 512kB RAM on that?

Just about anything you might do with a PDP-8.

Except run up a big electric bill. Easier to move too... :)

I knew TI was reluctant to produce data storage for the CC40 but that looks like a lot of work just to get DECTape running.

It is an impressive feat though.

ClassicHasClass
August 14th, 2015, 11:12 AM
Wafertape, ladies.
That is all.
(Yes, I have one of them. It works okay last I tested it, though I never used it heavily.)

JGardner
August 14th, 2015, 07:13 PM
Hi Krebizfan -

Thanks for the kind words.

I'm working on a Wafertape emulator - I also need a cartridge RAM which

allows loading an EA image. This should do it, and then some... :)

byates
August 15th, 2015, 05:53 AM
Any chance of a better look at the circuit? It would be interesting to see if it could be adapted to a TI-74.

JGardner
August 15th, 2015, 11:00 AM
Hi byates -

Unfortunately this scheme won't work with a TI-74. The CC40 cartridge port has two paging

bits available; as intended by the designers it will support 128K. I use those two bits as an

I2C bus to control a MCP23008 (a so-called 'port expander') to specify the high 4 bits of the

512K address. As presently constituted 23 bits are available; the scheme could address 8M.


The 74 cartridge port does'nt have paging bits; something else will have to be concocted.

There are multi-page '74 ROM cartridges; it's possible to use <Writes> to ROM to control

paging. For RAM, I think you'd need to decode a specific address and use that for page

control.

byates
August 15th, 2015, 12:32 PM
JGardner, thanks for the info. Looks like I will have to dig deeper if I want to expand it.

JGardner
August 15th, 2015, 01:42 PM
byates -

Perhaps the easiest thing to implement on the '74 would be to use the Dockbus port pins

to set the high address bits of cartridge RAM, using what TI calls "non-standard I/O mode",

aka BAV high & HSK low. Writes to the data port then appear immediately on the port out-

put pins.

Of course this means some wires (4) between the Dockbus port & the cartridge, and you'd

be limited to 512K, but I can't see any reason why it would'nt work fine, & the price would

be pretty hard to beat... Come to think of it, put a crowbar in your wallet & spring for an

extra wire & you could toggle BAV too, for a cool MB. :)


Think I'll try it - If you don't beat me to it...

JGardner
August 16th, 2015, 05:05 AM
I've attached a wiring list for anyone wishing to try their hand at big CC40 RAM cartridges.

Mine works - YMMV. Readers are welcome to contact me for a current, unhacked version

of the document. I'll make paging software available as well, "soon" - It's a bit, umm,

unpolished, at the moment. Have fun... :)

JGardner
August 17th, 2015, 10:49 AM
Decided to replace the MCP23008 with a 4094 shift register - Faster, simpler paging...

Revised the attachment to reflect the changes.

JGardner
August 18th, 2015, 04:26 PM
Paging - This works in an Assembler environment, but if called from BASIC crashes.

At a guess, changing pages boogers up the checksum; hopefully disassembling CTERP

will shed some light on this. We'll see...

Feel free to contact me for an unhacked version.

* Note that attachment has been edited to correct the customary blunders. Sigh...

JGardner
August 20th, 2015, 03:39 PM
...Paging... works in an Assembler environment, but if called from BASIC crashes...

Problem solved, I think. Hope to post code tomorrow.

Ever seen an old fat guy do the Teaberry shuffle? :)

JGardner
August 21st, 2015, 09:27 AM
For the guys who don't have a PCIF -

From the BASIC command line, enter the following line:

100 DATA #################################

Yep, that's 33 of them... Now, enter CALL DEBUG. In the monitor,

enter "D 4FD4". Press [ENTER].

Enter the bytes listed in the attachment, pressing [+] after each entry.

Your last entry should be >0A at >4FF4. Double-check your entries.

If it's not exactly as listed results will be "undefined"...


Exit the monitor, & from the BASIC command line enter:

110 PAGE=5

120 CALL POKE(20469,PAGE):CALL EXEC(20436)

130 PRINT "BREAK":PAUSE ! demonstrates that routine returns to BASIC


Once more, the DATA statement must be the first line in your pgm for the

offset addresses to be correct. The routine assumes it's running on an 18K

CC40 - If you have something else then you'll have to recalculate the CALL

addresses. The PAGE offset is 11 bytes from HIRAM; EXEC offset is 43.

If you use the routine from assembler it can go anywhere; put the Page #

in A and call the address @ >4FD7 (in this case.)

I'll post a loadable subpgm soon.


One more thing - If you do have a PCIF, you can enter the pgm as above,

and then SAVE it to PC - The DATA statement looks odd, but can be cut &

pasted without problems, as long as you don't inadvertently truncate it.


Have fun :)

JGardner
August 23rd, 2015, 04:38 PM
...enter CALL DEBUG. In the monitor, enter "D 4FD4". Press [ENTER].

Let's make that "enter "M 4FD4..."

Sorry about that... :(

brain
December 3rd, 2017, 07:11 PM
Sorry to resurrect an old thread, but I'v designed some RAM and ROM cartridges for the cc40, and I am interested in more details on how TI planned to use the two port pins.

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smp
December 4th, 2017, 04:50 AM
Sorry to resurrect an old thread, but I'v designed some RAM and ROM cartridges for the cc40, and I am interested in more details on how TI planned to use the two port pins.
...

By any chance, would your memory board work in a TI-74? Looks like a different form factor, but perhaps a converter to the TI-74 could be rigged up?

I've just acquired my TI-74, and I haven't started experimenting with it yet. I have an 8K RAM module (which most probably has a dead battery) as well as the Statistics and Finance ROM modules. I was figuring on opening the 8K RAM module to see if the battery might be replaced.

smp

PS: I have a large text file of CC-40 info by Dan Eicher dated 12/1/96. Have you seen that? It appears to have a wealth of info about interfacing to the CC-40 from back then.

JGardner
December 4th, 2017, 05:44 AM
Brain -

The article referenced by SMB is here:

http://ftp.whtech.com/hexbus_cc40_ti74/cc40%20ti74%20hexbus.txt

Bits 2 & 3 of the Peripheral File register P25 control the cartridge paging

bits present on pin 3 & pin 39 of the cartridge port.


SMB -

There are no equivalent paging bits present in the '74 cartridge port.

However Multi-page cartridges could be enabled by latching <Writes> to

a chosen address (>BFFF comes to mind) for use as the High Address for

a multi-page cartridge. The real problem is the unobtainable (AFAIK) '74

port connector (except by cannibalizing an existing cartridge)...

Hope this helps.

Jack

smp
December 4th, 2017, 06:45 AM
SMB -

There are no equivalent paging bits present in the '74 cartridge port.

However Multi-page cartridges could be enabled by latching <Writes> to

a chosen address (>BFFF comes to mind) for use as the High Address for

a multi-page cartridge. The real problem is the unobtainable (AFAIK) '74

port connector (except by cannibalizing an existing cartridge)...


That is exactly what I was thinking. I have these extra Finance and Statistics modules, as well as the 8K RAM with the dead battery. I also have a Dallas DS1220Y-150+ device. My initial thoughts were to rig that up as a 2Kx8 non-volatile memory, if I cannot get the battery backup to work on my 8K RAM module. Do you have any experience with taking these modules apart?

smp

brain
December 4th, 2017, 09:43 AM
By any chance, would your memory board work in a TI-74? Looks like a different form factor, but perhaps a converter to the TI-74 could be rigged up?

Not at present, but I can design a specific unit for the 74. The main problem is that one needs to find a source for the connectors for the 74.



PS: I have a large text file of CC-40 info by Dan Eicher dated 12/1/96. Have you seen that? It appears to have a wealth of info about interfacing to the CC-40 from back then.
Yep, dloaded it when I started on my efforts. It is missing a few items:


Pin 3 and 17 are listed as unknown, but JGardner's info notes they are PORT 25.2 and .3
ALATCH + .. is !OE
!WE is not defined (I found it by reverse engineering the RAM cart)
A14 is shown inverted, but putting the cc40 on my scope does not show any such inversion.

brain
December 4th, 2017, 09:50 AM
Brain -

The article referenced by SMB is here:

http://ftp.whtech.com/hexbus_cc40_ti74/cc40%20ti74%20hexbus.txt

Bits 2 & 3 of the Peripheral File register P25 control the cartridge paging

bits present on pin 3 & pin 39 of the cartridge port.


Understood, but I am trying to sort out how it was decided that the two bits were to be used for paging. Are there routines in the ROM using them in that way?




SMB -

There are no equivalent paging bits present in the '74 cartridge port.

However Multi-page cartridges could be enabled by latching <Writes> to

a chosen address (>BFFF comes to mind) for use as the High Address for

a multi-page cartridge. The real problem is the unobtainable (AFAIK) '74

port connector (except by cannibalizing an existing cartridge)...

Hope this helps.

Jack

I'm less concerned about paging bits, as I have created a 512kB ROM/512kB RAM cart that includes a small CPLD. Since all signals are present on the bus, it is trivial to decode a specific address (not in the CART ROM or CART RAM space) and use that register to bank the RAM and ROM. Any externally accessible memory location can be used.

I have a few goals:


create 2 banking registers. One for the lower 16kB of memory, and one for the upper
Create a config register for the two banks (00 = nothing,, 01 = rw ram, 10 = read only ram, 11 = rom)
See if I can map memory into the various unused places in the memory map from the cartridge space, to completely fill the unit with RAM

acadiel
December 5th, 2017, 04:47 PM
I added some .02 to the CC-40 thread on Atariage:

http://atariage.com/forums/topic/255728-the-compact-computer-40-cc40/?p=3905368

I'm not quite too sure how it did it, but the Editor Assembler cart was 64K and was paged between two 32K banks. Ksarul will have to tell us how A15 was hooked up, but the cart was super simple. One EPROM and one resistor. I'm guessing one of the CC-40 pins was hooked up to A15 on the 27512, and toggled it somehow to switch between the two 32K banks.

Once switched though, if I remember how I dumped it correctly, it stayed in that 32K bank when you quit the program. When you ran the other program in the cart, it switched banks and ran it. Part of the cart has Editor Assembler and part of the cart has Memo Processor. My guess is that they had to modify the cartridge header in both carts, or that the CC-40's ROM by default can scan multiple banks for the program headers itself (and in this case, I'd have to do a DIFF on Memo Processor in EA vs Memo Processor stand alone to prove it's the same or not.)

Edit: The memo processor binaries in the stand alone and the EA cart are both identical. I'm surmising the CC-40 ROM can do paging built in and determine if there are multiple 32K banks to scan. To prove or disprove this, we would have to put two 32K images in a 64K EPROM and hook it up like the EA cart and see if it actually will run either program.

brain
January 7th, 2018, 11:52 AM
The new version of the ROM carts has the PORT25.2 pin connected to the A15 line (via a jumper, not connected by default. By soldering it shut, you can test.

ndp630
January 7th, 2018, 02:05 PM
I just bought a cc-40 on eBay today. Are either the ram cartridges close to release, or maybe even a multicart of programs?

NilsFor
January 23rd, 2018, 10:22 PM
I think you can easily check that on eBay in "similar goods", they always pop in whan I browse.

JGardner
March 20th, 2018, 04:32 AM
...I am trying to sort out how it was decided that the two bits were to be used for paging. Are there routines in the ROM using them in that way?

Sorry I missed this 1st time through... I loaded Acadiel's dump of his

EA cartridge into a breadboarded 128K RAM which used the pins in

question for paging bits. The 64K EA image worked as advertised, so I

think it's reasonable to assume the presumptive paging bits have been

identified. Also, one of the CC40 User Manual Appendices refers to P25

as the "Page Control Register" - RTFM strikes again... "8)

p.s. - Toggling P25.2 & 3 with DEBUG toggles the appropriate cartridge

port pins - QED...