PDA

View Full Version : IO ports to memory DMA - timings



newold86
November 11th, 2017, 01:51 AM
While playing with DMA transfers for my card (http://www.vcfed.org/forum/showthread.php?46427-Modern-XT-compatible-PC-on-FPGA-with-real-8088&p=482366#post482366) I ran into strange issue. Hopefully will manage to explain clear enough what I'm looking for :)

So, at the first glance the data transfer from the SD card to memory is working properly, but then I noticed that the data are shifted by one byte. Short investigation using a logic analyzer revealed improper timing of the memory write - I provide the proper data to the data bus too late. I knew I can't provide the byte immediately after beginning of the DMA operation (need some time to receive the byte via SPI), so holding IORDY until the data is ready. This approach is working perfectly on regular CPU read, and almost working on DMA cycle. Almost - because 8237 properly handles low IORDY and waits for the data, but looks like the memory still writes the data at the very beginning of the DMA cycle, even if the MEMWn goes back to high after the correct data on the data bus and IORDY released...

Basically, I have two issues here:

1. Of course, it's possible to change the design of my SD card module to have the data ready before requesting DMA. Unfortunately, besides of significant complexity, it will reduce the efficiency, and will not look so simple and elegant :)

2. More important question - where can I find timing requirements for this type of operations ? It's not 8237 issue - we are talking about memory system. Basically, how fast after MEMWn goes low I need to provide valid data to data bus, and when exactly the write operation happens (so, when can I remove the data from the bus) ? Searched a lot of sources, couldn't find anything...

newold86
November 12th, 2017, 10:20 AM
Spent some time looking at XT schematics - can’t believe what I found... Seems the memory write cycle during DMA does not depend on CHRDY signal at all - actual writing always happens on fixed timing after MEMW goes low, even if CHRDY at that moment is low...

eeguru
November 12th, 2017, 03:05 PM
You have plenty of block RAM. Once a sector is requested from storage, kick off your SDIO state machine and push the data into a FIFO. Once you reach a low water mark (can be just a few bytes), assert DMA request. We're not taking about the most amazingly fast host machines here.

newold86
November 13th, 2017, 12:39 AM
You have plenty of block RAM. Once a sector is requested from storage, kick off your SDIO state machine and push the data into a FIFO. Once you reach a low water mark (can be just a few bytes), assert DMA request. We're not taking about the most amazingly fast host machines here.
Of course, it's very straightforward solution. But this approach has a number of issues. Most important - I was considering designing a relatively low cost and easy to solder SD card board on 5V tolerant CPLD. Unfortunately, there is no such CPLD with built-in memory...

Chuck(G)
November 13th, 2017, 07:35 AM
Wouldn't a 5V tolerant MCU cost about the same and have local memory? It might even have a 4-wire SDIO interface.

newold86
November 13th, 2017, 08:05 AM
Wouldn't a 5V tolerant MCU cost about the same and have local memory? It might even have a 4-wire SDIO interface.

Interesting and quite a logical idea ! I have almost zero experience with MCUs, but it's a great excuse to play with them :)