Well while clh333 is still to reply I'll throw in my thoughts as I voted for that line too. First, because you didn't give the option separately, I'm treating "CPLD" as "CPLD/FPGA" - whatever...
There is another very recent thread on the forum where we did exactly this and tested the IEEE port in isolation from anything else. The other thing to check is that you have the IEEE cable in the...
Set ourselves the goal of getting space invaders running! Dave
One of the documents I read yesterday I am sure had the bit patterns for the character generator in it. Dave
If you haven't already, force CMOS clear. You can clock a 40 MHz part at 33 MHz and timing will loosen up some. One 72-pin SIMM is enough for POST to succeed. IIRC you need FPM not EDO RAM. I...
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Well while clh333 is still to reply I'll throw in...
Well while clh333 is still to reply I'll throw in my thoughts as I voted for that line too.
pjhacnau Today, 02:59 AMFirst, because you didn't give the option separately, I'm treating "CPLD" as "CPLD/FPGA" - whatever...