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  1. Replies
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    199

    Link? lol

    Link? lol
  2. I don't understand. The iCE40up5k is not a 5V...

    I don't understand. The iCE40up5k is not a 5V nor 5V tolerant part. How are you doing level translation?
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    Don't worry about 0-wait under 1MB of RAM. 2...

    Don't worry about 0-wait under 1MB of RAM. 2 cycles vs 3 is 50% faster but you are never going to make a 286 into a speed demon. Most era-correct cards that supported 0-wait only did it for...
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    You can achieve 1 wait but not zero unless you...

    You can achieve 1 wait but not zero unless you decode LA and assert combinatorially within 1 CLK in combination with asserting ZWS# within 1 cycle of the strobe assertions.

    BTW, your .oe logic is...
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    Saw that video today as well in my YouTube...

    Saw that video today as well in my YouTube suggested links. Was like a time machine.
  6. Are you crazy? No one has that kind of money...

    Are you crazy? No one has that kind of money...
  7. Is there anyway they can do a proper double-tall...

    Is there anyway they can do a proper double-tall male header with offset shroud like on the original RAM expansion Plus board? That way, whatever designs come out of this thread could be a proper...
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    When you attach images to this forum, it...

    When you attach images to this forum, it significantly reduces the resolution for storage. Nothing is readable anymore. To quote Dave Matthews, "...all the little ants are marching. Red and black...
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    Your text images got decimated...

    Your text images got decimated...
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    This is a gen-1 AS/400. Since the series...

    This is a gen-1 AS/400. Since the series introduction pre-dates Linus writing the first pass at a kernel by 3 full years, I'm pretty sure it doesn't. It would run an early version of OS/400 that...
  11. I'm not sure how it's any different or even...

    I'm not sure how it's any different or even better than the above - which can also fit in a 22v10 with a lot lower propagation time. The scanless input matrix is clever though.
  12. Dwight, I must be confused. We've already...

    Dwight, I must be confused. We've already discussed an PROM only design. You have to have some state elements to shift reporting of keys in different scan lines over in time. I fail to see how...
  13. Actually I'm wrong. I checked the data sheet. I...

    Actually I'm wrong. I checked the data sheet. I guess my memory is suffering from bit-rot.
  14. Worst case interrupt latency on an ARM CM3/4 is...

    Worst case interrupt latency on an ARM CM3/4 is 27 cycles or 169 ns before you get to the first instruction of the ISR. AHB data movements can cause processor waits as well. Not saying it wouldn't...
  15. Yes I know. I've already posted complete source...

    Yes I know. I've already posted complete source code for a single chip solution running on a ATF1502 in this thread.



    I don't follow. If the original hardware MCU is scanning the matrix by...
  16. SPLDs will not work unless you know the scan...

    SPLDs will not work unless you know the scan direction before hand. There is only one global OE on a 22v10 for example. You can't high-Z individual pins. But it doesn't matter if you know which...
  17. You can do it with a logic probe as well. When...

    You can do it with a logic probe as well. When no keys are being pressed, one side of the matrix will be at a static logic level (likely +5V). The other side of the matrix will have a repeating...
  18. This thread has consumed my consciousness this...

    This thread has consumed my consciousness this weekend :( The more I think about it, the more I'm certain the BASIC stamp, Arduino, relay solution or anything similar is never going to work. It's...
  19. On the output side of things, they are all inputs...

    On the output side of things, they are all inputs and outputs. The OUT_COLx have terms that depend on OUT_ROWx and vice-versa. They idea is you wouldn't have to determine the scan direction of the...
  20. Couple final thoughts. If you use a MCU, it has...

    Couple final thoughts. If you use a MCU, it has to be clocked significantly faster than the scanning MCU - which is essentially doing I/O port write of the new column pattern and an immediate I/O...
  21. What I mean is.. what's next? Take key press #1...

    What I mean is.. what's next? Take key press #1 for example. It's in a different scanning row than the original matrix. I understand what you are doing with the address inputs to the ROM. ...
  22. I don't really understand what you are proposing....

    I don't really understand what you are proposing. You haven't detailed it well enough imo.

    Even if you take advantage of the fact there is a common dimension in both matrices (3) and leverage the...
  23. I don't know. That's why I said 'assuming it's a...

    I don't know. That's why I said 'assuming it's a scanning matrix'. It needs to be checked.

    But here is some rough/untested CUPL that illustrates my concept. External pulls-up would have to be...
  24. Assuming it's a scanning matrix, I don't think it...

    Assuming it's a scanning matrix, I don't think it matters which side is driving from the solution perspective of using a PLD (PROM is different). The detection side will be individually pulled to a...
  25. Not true. It looks like you were running...

    Not true. It looks like you were running jrconfig.sys which makes a permanent memory reservation in order to move the starting address past the lower 128K for speed. Of course things like the...
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