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Type: Posts; User: dave_m

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  1. Replies
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    With three chip selects in the PIA, it may too...

    With three chip selects in the PIA, it may too difficult to get a good trigger to check the data lines using the scope. Let us ponder on other tests.
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    Signals looks OK to the PIA, the chip selects are...

    Signals looks OK to the PIA, the chip selects are connected properly to the PIA. The 50 Hz is not there because CRT Controller (6545) is not initialized (due to NOP test). But as far as data lines, a...
  3. Hutch, Please tell us more about the equipment...

    Hutch,
    Please tell us more about the equipment you used to find the problem.

    I don't have a digital scope, but you say the one you used had a VGA video output signal that you were able to capture...
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    The UB12 PIA that handles the keyboard and...

    The UB12 PIA that handles the keyboard and interrupt is in the range of $E810.
    It requires /SEL E Low, X8XX High, and address line A4 high.


    Those signals are on UB12 pin 23 (/I/O), UB12 pin...
  5. OK, I was thinking that there was a bad solder...

    OK, I was thinking that there was a bad solder joint between C6-pin11 and C7-pin1 causing the line to float and making C7 pin3 to toggle at the clock rate, but you found that the C6 pin11 output was...
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    Yes, it looks fine. I was hoping a chip select...

    Yes, it looks fine. I was hoping a chip select problem at the ROM(UD7) was stepping on the PIA and keeping it from being properly initialized and therefore not issuing interrupt requests. Is it worth...
  7. Yes, J=0, K=1 then Q is Low at next clock. ...

    Yes, J=0, K=1 then Q is Low at next clock.


    Look right at C7 pin 1, the J input. Is it high or floating (2.6V) when its source C6 pin 11 is Low?

    If Low, then the Q can not be toggling unless...
  8. You are not paying attention. C7 pin 1 (J input)...

    You are not paying attention. C7 pin 1 (J input) is supposed be connected to C6 pin 11 which you say is Low. Therefore the output of the F/F can not be toggling unless the J input at pin 1 is High or...
  9. From this it seems that the J input at C7 pin1 is...

    From this it seems that the J input at C7 pin1 is going open. Reflow the solder joint.
  10. Replies
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    The photos of your message #20 showing the chip...

    The photos of your message #20 showing the chip selects did not attach properly and could not be seen. I assumed they were OK, but we need to see them with the addition of a signal called x8xx which...
  11. I don't think it is possible to change the title.

    I don't think it is possible to change the title.
  12. Replies
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    If you have a scope, check for the 50 Hz...

    If you have a scope, check for the 50 Hz interrupt before and after.
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    You might want to just cut the IRQ line at pin 21...

    You might want to just cut the IRQ line at pin 21 of the VIA. I don't think it is used. After checking for proper operation, you can tack it back in place.
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    The keyboard PIA UB12 is the only chip that...

    The keyboard PIA UB12 is the only chip that issues an interrupt. The Vertical Drive signal goes to a UB12 input at pin 18. The PIA is initialized to issue an /IRQ when it sees a pulse on pin 18. Can...
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    The keyboard is not needed for the cursor. You...

    The keyboard is not needed for the cursor. You may not yet be getting the 60 Hz interrupt. A Motorola 6820 or 6821 may be easier to find than a 6520.
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    Good work so far. Are you getting a blinking...

    Good work so far. Are you getting a blinking cursor proper keyboard response?
  17. OK, now I understand. Your screen only goes out...

    OK, now I understand. Your screen only goes out once in a while and is mostly good. That is tricky to troubleshoot.
  18. So you have a good Vertical Sync most of the...

    So you have a good Vertical Sync most of the time? The Vertical Sync will be a about a two mS negative pulse every 16.66 mS (60 Hz). If you don't have this, the state sequencer (B6 flip-flops) is...
  19. Hi Hutch, You don't see C7-pin 3 pulse because...

    Hi Hutch,
    You don't see C7-pin 3 pulse because it goes low (and stays low) when the State Sequencer stops/hangs as it is the clock to the state sequencer (flip flops B6). No clock, no state change....
  20. Andy, Yes it could as it might keep the main...

    Andy,
    Yes it could as it might keep the main counters D6 and D7 from reaching the terminal count (detected by D8-pin3) to increment the sequencer.

    The counters D6 and D7 should have been the...
  21. A1-pin2 (Reset) must be LOW to allow the counter...

    A1-pin2 (Reset) must be LOW to allow the counter to run. If it is pulsing high a lot then the counter will stay reset. If pin 2 is LOW most of the time as it should be, then I agree the counter may...
  22. No, there is little circuitry in common between...

    No, there is little circuitry in common between HSync and VSync. VSync is the output of a complicated sequencer and HSync is an output a simple countdown circuit. They only have part of the clock...
  23. A little confusing, but not a problem. It is...

    A little confusing, but not a problem. It is shown as a 'demorgan' of a NAND gate and is equal. Actually shown for clarity as this gate is used in this circuit as an 'OR' function with negative...
  24. If the B6 outputs were going at that rate, you...

    If the B6 outputs were going at that rate, you would see a vertical sync pulse every 16 uS instead of about 16 mS. The screen would definitely have problems/collapse!

    EDIT: If so that would lead...
  25. Hutch, But then you said you COULD see the...

    Hutch,
    But then you said you COULD see the compliment signal out of C7- pin 2?? That should just look like a negative glitch compared to the positive glitch from C7= pin 3. Maybe you are just not...
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