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View Poll Results: Which connection options would you prefer?

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  • As original XT-IDE, with a 40-pin header only

    4 10.53%
  • With a 44-pin header and board space to mount a 2.5" IDE HDD (i.e. a hard-card)

    7 18.42%
  • With an optional Compact Flash socket (as master or slave) and a 40-pin header

    26 68.42%
  • With a Compact Flash socket only

    1 2.63%
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Thread: Forthcoming XT-IDE Board - Cast Your Vote

  1. #1

    Default Forthcoming XT-IDE Board - Cast Your Vote

    Ian at Dangerous Prototypes has ported the existing XT-IDE board design to a 'CPLD' based design, which means that the whole circuit design can be programmed. In other words, as well as ROM changes, circuit design changes can be implemented by reprogramming it!

    So far two prototype boards have been made and have worked with every disk and compact flash card so far tested (only about 10 devices, but a promissing start) and it works fine in PC/XT and higher-spec machines too (tested up to Pentium III I think).

    Currently a v2 board is being drawn up, which will have even less components than the prototype, but there are several ideas being thrown around. Hence I would like to collect please opinions on it - please cast yor vote!

    For those interested:


  2. #2
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    The Hard Card is a neat idea, and would be nice. But I think ultimately it would be too limiting, same with only putting a CF slot on the card.

    The CF and 40 pin option is nice because it allows for quite a bit of flexibility in storage options, plus CF cards are easy to find in any size needed, and plugging one in makes it a solid state drive for an 8 bit PC which is pretty cool.

    IBM 5160 - 360k, 1.44Mb Floppies, NEC V20, 8087-3, 45MB MFM Hard Drive, Vega 7 Graphics, IBM 5154 Monitor running MS-DOS 5.00
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  3. #3
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    I would like the CF option, a nice and elegant solution for the 21st century.

  4. #4
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    CF is 21st century? From my understanding, they're on the way out, being replaced by higher-capacity, cheaper, and ever-faster SDHC cards, whether full-size or micro. About the same for 44-pin vs 40-pin. Unless you have alot of laptop spares, 44-pin cables aren't usually in the parts bins. 40-pins are, as is the ever-present 44->40 pin 2.5" adapters.

    That said, I'm happy with anything, and whatever keeps costs down. If a 40-pin IDE is on there, I can add an IDE->CF adapter cheaply (I have several). If a 44-pin IDE, I have a cable in the parts bin. If a CF, I have a spare 4gb microdrive out of an iPod mini upgrade and/or a few different CF card sizes.

    Although I wouldn't be ordering Ian's board until after the v2 XT-IDE comes out. I want to see what Hargle, Andrew, et. al. have come up with.

    And I think that there's room on Ian's board for a floppy simulator if someone was on-board to program software for it. Now THAT would be a cool adapter.

    (as I'm still drooling over Chuck's proof-of-concept)
    ---
    Currently seeking:
    * Roland MPU-401/AT (with daughter card header)
    * Magitronic K-156 Keyboard (5pin DIN w/ XT-AT switch)
    I also collect PC and C64 Sierra On-Line software!

  5. #5
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    Quote Originally Posted by pearce_jj View Post
    ...which means that the whole circuit design can be programmed. In other words, as well as ROM changes, circuit design changes can be implemented by reprogramming it!
    That's not quite accurate. They didn't add the latches to the CPLD nor did they route most of the signals through it. The CPLD in his design is only being used as an address decoder. It means changes similar in scope to the 'Chuck mod' have to still be done with wire rework. I routed everything through the JR-IDE board's CPLD. All IDE pins and all relavent bus pins are connected directly to 5V GPIOs and everything is through hole. I have more proving out to do on the JR-IDE board this weekend then I need to make all the necessary changes for a P2 board spin early next week. I'm also planning a P1 spin of an ISA version (with only IDE and Flash disk) at the same time. The design files for the JR-IDE P1 are here and the discussion thread (very long) is here. I'll be updating things next week (and moving the site) to include the PLD code once the P2 design is finalized. JR-IDE has the 'Chuck Mod' implemented for writes as well as reads and uses memory mapped I/O. DMA could be doable for the ISA version as well as I experimented with a self bus-mastering version for the JR.

    The current layout I have for the ISA CPLD board is literally a single chip + header + a couple offset socket pads for either a 28 or 32 pin 27xx/28xx ROM (28 pin) or 39SF0x0 Flash (32 pin and much much cheaper).

    The JR version also has a flush PCB board mount for a 2.5 hard drive (screwed in from the back of the PCB). I ran out of real-estate in my Eagle license to add a 40 pin .1" header as well. With CF, you're back into SMD and the tighter pitch of most sockets combined with the proximity to plastic is going to make soldering them more challenging with an iron vs hot air.
    "Good engineers keep thick authoritative books on their shelf. Not for their own reference, but to throw at people who ask stupid questions; hoping a small fragment of knowledge will osmotically transfer with each cranial impact." - Me

  6. #6

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    Quote Originally Posted by eeguru View Post
    That's not quite accurate...changes similar in scope to the 'Chuck mod' have to still be done with wire rework
    We've demonstrated the v1a board with Chuck-mod via reprogrammed CPLD - possibly at crossed-purposes though?

    Quote Originally Posted by eeguru View Post
    I routed everything through the JR-IDE board's CPLD....JR-IDE has the 'Chuck Mod' implemented for writes as well as reads and uses memory mapped I/O
    I'm very interested in your implementation and how the circuit design has been modified to run the enhanced writes! So thanks for the links, I'll have a good look through later. The "100% CPLD" approach is what the v2 board being discussed here is going for also.

    Quote Originally Posted by eeguru View Post
    The JR version also has a flush PCB board mount for a 2.5 hard drive (screwed in from the back of the PCB).
    This is very neat for sure, and I like neat but I'm not sure it makes the board more future proof than CF, and anyway the cheapest 2.5" IDE HDD is 10x the price of a (1GB) CF card (of course many of us will have such drives sitting about though). As the recent range of Canon Pro bodies are CF based, hopefully it will be around for some time to come yet.

    Thanks for all the input thus far!!

  7. #7
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    Quote Originally Posted by pearce_jj View Post
    We've demonstrated the v1a board with Chuck-mod via reprogrammed CPLD - possibly at crossed-purposes though?

    I'm very interested in your implementation and how the circuit design has been modified to run the enhanced writes! So thanks for the links, I'll have a good look through later. The "100% CPLD" approach is what the v2 board being discussed here is going for also.
    I was using Chuck's change as a flexibility example. For him to get the registers ordered to correctly fetch the lower bus value and then the upper bus latched value, he had to cut and switch two address lines. Those address lines are not routed through the CPLD in the DP design. So it isn't ideal in a sense. To do things ideally, you would have the 24 necessary independent IDE signals, the 33 necessary ISA signals, 4 DMA, ROM CS, and possibly bus clock routed to pins on a PLD (63 total requiring a PLCC-84 or TQFP-100). Then soft code everything in the middle. That's what I've tried to do. And by using a true 5V part with a high drive current, there isn't a need to add separate buffers for IDE either. You can literally do it with one chip and change 100% of it. I apologize for this turning into a design discussion about architecture. And there's already been a number of discussions on PLD part choice and positions well voiced.

    Ian has done nice work and I definitely thank him. But I think there is still a little room for improvement. Just adding my $.02
    "Good engineers keep thick authoritative books on their shelf. Not for their own reference, but to throw at people who ask stupid questions; hoping a small fragment of knowledge will osmotically transfer with each cranial impact." - Me

  8. #8

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    I appreciate your input on this. Just confused about the chuck-mod, as the DP design does do the expected 230KB/s with it (and without any physical changes to the board). But then, it doesn't take much to confuse me

  9. #9
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    Ian included Chuck's address lines changes in his board version. However if anything needed to be changed again, exacto and iron time.

    I just registered over a DP forums and continuing the design discussion there.
    "Good engineers keep thick authoritative books on their shelf. Not for their own reference, but to throw at people who ask stupid questions; hoping a small fragment of knowledge will osmotically transfer with each cranial impact." - Me

  10. #10
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    I'm with the SD/SDHC idea. Cheap, small and definitely what everyone seems to be using. I view CF in the same light that I view PATA--yes, you can get it, but it's definitely not on the leading edge. I just picked up a bunch of "universal flash card readers"--and CF isn't one of the card types supported. Since the protocol is serial, the incremental expense of adding another CF socket is pretty much the cost of the socket.

    On the other hand, microcontrollers with integral USB support capable of hosting USB flash drives are now inexpensive (and 3.3V, but that's a different issue) and readily available. That aspect does hold a certain attraction, as USB ports are everywhere and heck, USB flash drives are given away as door prizes now.

    These retrofits are becoming harder. I was reading about a new line of DSP µCs that are inexpensive and fast. Then I started reading the specs--1.8V (okay, I can deal with translating to 5V logic; it just gets harder) and available only in fine-pitch BGA (definitely not in the DIY category).

    And who's this "Chuck" guy, anyway?

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