For those that may be interested I have written up a detailed description and construction details of the new “MSDOS Support S-100 bus Board that Andrew & I have completed. A while back we decided to try and put together a kind of "catch all" S-100 board that would cleanup some loose ends need to easily run MSDOS on an S-100 system and with our future CPU boards. Here is what we could fit on one S-100 board.

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In Summary the board contains:-

8259A PIC
First of course we need an 8259A interrupt controller. The chip is hard wired to ports 20H and 21H -- ports almost ever PC 8259A in the world is hard wired to these ports!

One very useful feature we found on one of our earlier PIC-RTC board was the LED bar that stretched any one of the eight S-100 bus interrupt pulses out to a visible light flash. I added this useful debugging feature to our MS-DOS board.

This is the most important component on the board. This chip is 100% software compatible with the PC-AT CMOS RTC chip and one can access the chips onboard RAM. On all PCs the RTC is on IO ports 70H and 71H. This is hard wired as such into our board.

8254 Timer
All PC's use this timer. It is kind of underutilized though. Of the 3 timers on the chip, one is used for the system tick. Another is used to generate sound on a small speaker. The speaker is driven by a 75477 chip. The PC uses an unusual clock frequency (1.193MHz) to drive the timer. We generated this frequency using a common 14.318 MHz TV oscillator and a 74LS92 divide by 12 counter. The counters can be configured to trigger any one or the S-100 bus interrupt lines (as on the PC).

EEPROM Circuit
For 8086 boards that do not have (or have a limited) an onboard boot ROM capability, we added two sockets and support circuitry to support 28C64 and 28C256 EEPROMS. The EEPROMs can be located anywhere in the S-100 address space so they could be used for video or network card drivers.

Two Wait State Circuits
The board has a wait state circuit for the above dual 16 bit wide EEPROMS. From 0 -8 wait stares can be added for any CPU access.

However the board has a second wait state circuit that is a bit more unusual. This circuit allows you to insert 1-8 wait state "holes" anywhere in the S-100's address space to accommodate a pocket of slow access RAM