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Thread: Intel iSBC 386/AT or MicroSystem/AT 301 motherboard jumper settings

  1. #11
    Join Date
    May 2006
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    Melbourne, Australia
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    Quote Originally Posted by modem7 View Post
    No different to the IBM AT. 512KB-640KB provided by way of their optional '128KB Memory Expansion Option' card.
    I figure that it was because of limited real estate on the motherboard.
    Quote Originally Posted by mR_Slug View Post
    This certainly makes sense on the AT with a 16-bit bus, However on a 386 with a 32-bit memory bus, There is the first 512KB with 32-bit access. Then 128KB with 16-bit access then, from 1024KB onwards 32-bit access. IF something like say OS/2 is unaware of the slow 128KB range, AFAIK it will slow down things a bit.
    You are right. I forgot that we are dealing with a 386.

  2. #12

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    Hi, I've been probing away and I seem to have workout some of the jumpers. One jumper I am trying to eliminate from the memory configuration is a 3 pin jumper next to the keyboard connector:
    Code:
            ---
            |*| E1
            |||
            |1| 
            ---    
             1  E3
    E1 goes to pin4 (RESET) of the keyboard controller.

    Both E2 and E3 are connected together regardless of jumper configuration and connect to pin 3 of the keyboard connector. Which is supposed to be not used by the keyboard. I have tried to find another place on the motherboard that has continuity to this, but as of yet no luck. It does not stop the no keyboard present error. Anyone have any idea?


    Back to the memory, I have decoded some jumper settings related to the ram:
    Code:
            ---
            |1| E28      G = Ground
            |||
    E29   G |1|          1, 2, 3 = Numbered pins have
            ---    	     continuity, with pins of the 
          G |2|	     same number. This holds true
            |||          whether the jumpers are ins-
          G |2|          talled, in the configuration
         ------          shown  to the  left,  or re-
    E35  |3--3| E36      moved.
         ------
    The only other jumper configuration that makes sense AFAIK is:


    Code:
              
             1  E28      G = Ground
         ------
    E29  |G--1|          1, 2, 3 = Numbered pins have
         ------    	     continuity, with pins of the 
         |G--2|	     same number. This holds true
         ------          whether the jumpers are ins-
         |G| 2           talled, in the configuration
         |||             shown  to the  left,  or re-
    E35  |3| 3  E36      moved.
         ---
    I've not experimented with connecting groups 1 to 2 and groups 2 to 3.

    Adjacent to this jumper block is a 916C103x2PE chip. AFAIK, this is a DIP resistor network. E28 and E30 lead to pin 5 of this chip. E32 and E34 lead to pin 6, and E35 and E36 lead to pin 7. Cant find a datasheet for this chip.

    With the memory card in J19 (the slot on the left), Connecting E29 to E30 produces this message on boot up:

    data line failure at 100000-10FFFF

    Adding either, or both of the other jumpers in the configuration above produces the same result. With E29-E30 removed, the system does not report any memory error, nor count any extended memory. If I install the memory card in J20 (the slot on the right) the jumpers seem to have no effect.

    So from this I am guessing that I have managed to enable the memory card, and found the first slot, but it seems to have an error in the first 64K?

    Occasionally i get this message on bootup:

    Memory write/read failure at 100002, read FF30 expecting FF10.

    At present, this error seems like an intermittent problem. I cant easily reproduce this error. With either error, it would appear that there is a faulty ram chip on the memory card.

    The chips are labeled TMS4256-12XL so they are 41256 class. At present all i know about the ram card, is that the configuration is interleaved.

    Does anyone know which chip may be located at 100000h? Or failing that how to work out which chip is located at 100000h? Anyone have any experience with this sort of thing? I am at a loss to know where to start. Bear in mind all the RAM is soldered down, limiting my options a bit. Is there a way to test soldered ram chips?

    Thanks

    Andrew

  3. #13

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    I asked Chuck McManis about this, and I will quote: "Andrew, the poster doesn't seem to realize that there are 16 (or 32) chips at location 0x100000 (1MB) according to his last entry on the board.

  4. #14

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    I'm not sure how long is too long to revive an old thread. But here goes anyway. Please let me know if its better to start a new thread.

    I have had a few questions PM'd to be about this system and I was eventually able to get the thing working. The short answer is that I worked out the functionality of the RAM card and still ended up mass desoldering chips using a paint stripper gun and socketing them. It's now working. I plan to document the board in some detail in the future. It will be along the lines of the Ardent Tools of Capitalism pages for the PS/2's.

    @yuhong - My question "Does anyone know which chip may be located at 100000h" was a bit sloppy.

    The long (rambling) version:
    The board responds in 32-bit chunks, or 64-bits (32-bit chunk followed by another, it's interleaved). So given an input address with a RAS+CAS format, IIRC first the board responds with all the bits from the chips on the right giving 32-bits, and 60ns later does the same with all the chips on the left.

    However before probing LITERALLY EVERY SOLDER POINT I didn't know how the physical RAM layout mapped to the logical one. It seemed reasonable to say that all the chips on one side were accessed first, followed by the other side, but I didn't know for sure. It could have been some other configuration.

    The board is effectively addressed in 64-bit chunks. change one bit in the address sent with the RAS or CAS, and the board responds with a new 64-bits sent in 2 32-bit groups.

    the "Memory write/read failure at 100002, read FF30 expecting FF10." gives indication that the BIOS message is numbered in bytes. 100000h is 1024KB. So 100000h refers to the first byte, 100001h second, 100002h third and 100003h fourth. The error "read FF30 expecting FF10" along with "100002" gives indication that the bios is counting in words. So 100000h refers to the first word 100002h the second. That is, it's never going to respond with the message "Memory write/read failure at 100001..." It's only ever going to show an even number.

    Confusion #1: numbering in bytes, counting in words. To an ASM hacker, this is entirely logical when you consider the AL AH AX registers. To a simpleton trying to replace a RAM chip, it's confusing.

    So from this we can determine that at address 100000h there are only 8 chips. (lets forget the interleaving for the moment)

    There is still a problem of which 8 chips? and of those 8 which is bad?
    Code:
    FF30 is: 11111111 00110000, and 
    FF10 is: 11111111 00010000, xor'd giving
             00000000 00100000
    and this all starts at 100002h. So looking at it from a 32-bit perspective, at 100000h:
    Code:
    00000000 00000000 00000000 0010000
    Confusion #2: numbering in bytes, counting in words, with a dword interface. To an ASM hacker, this is entirely logical when you consider the AL AH AX EAX registers. To someone realizing they're out of their depth, trying to replace a RAM chip, it's confusing.

    Confusion #3: By the way it's interleaved! <facepalm>

    So now we have:
    Code:
    00000000 00000000 00000000 00000000 00000000 00000000 00000000 00100000 or perhaps:
    00000000 00000000 00000000 00100000 00000000 00000000 00000000 00000000
    On top of this I didn't know which bit was the LSB, so you could inverse the two previous patterns. And on top of that there are also parity chips. So if we try mapping this to the card. Lets assume all the parity chips are on the bottom, and the LSB is the top left we can mark an x on the bad chips matching each of these patterns. Problem is maybe the LSB is the the bottom right, or maybe it starts at column 4 at the top (or bottom), maybe it counts from column 4 at the top to column 1, or perhaps the parity bits are at the top transposing my x marks the spot pattern one chip up. Essentially what I came up with was this:
    Code:
    P? = Parity?  x = Likely spot  ? = possibility
     ______________________________________________________________________________________________________  ___
    | _____   _____   _____   _____      _____   _____   _____   _____      _____   _____   _____   _____  ||
    ||_P?__| |_P?__| |_P?__| |_P?__|    |_____| |_____| |_____| |_____|    |_P?__| |_P?__| |_P?__| |_P?__| ||
    | _____   _____   _____   _____      _____   _____   _____   _____      _____   _____   _____   _____  ||				
    ||_____| |_____| |_____| |_____|    |_____| |_____| |_____| |_____|    |_____| |_____| |_____| |_____| ||
    | _____   _____   _____   _____      _____   _____   _____   _____      _____   _____   _____   _____  ||				
    ||__x__| |__?__| |__?__| |__x__|    |_____| |_____| |_____| |_____|    |__x__| |__?__| |__?__| |__x__| ||
    | _____   _____   _____   _____      _____   _____   _____   _____      _____   _____   _____   _____  ||			
    ||__x__| |__?__| |__?__| |__x__|    |_____| |_____| |_____| |_____|    |__x__| |__?__| |__?__| |__x__| ||
    | _____   _____   _____   _____      _____   _____   _____   _____      _____   _____   _____   _____  ||				
    ||_____| |_____| |_____| |_____|    |_____| |_____| |_____| |_____|    |_____| |_____| |_____| |_____| ||
    | _____   _____   _____   _____      _____   _____   _____   _____      _____   _____   _____   _____  ||				
    ||__x__| |__?__| |__?__| |__x__|    |_____| |_____| |_____| |_____|    |__x__| |__?__| |__?__| |__x__| ||
    | _____   _____   _____   _____      _____   _____   _____   _____      _____   _____   _____   _____  ||				
    ||__x__| |__?__| |__?__| |__x__|    |_____| |_____| |_____| |_____|    |__x__| |__?__| |__?__| |__X__| ||
    | _____   _____   _____   _____      _____   _____   _____   _____      _____   _____   _____   _____  ||				
    ||_____| |_____| |_____| |_____|    |_____| |_____| |_____| |_____|    |_____| |_____| |_____| |_____| ||
    | _____   _____   _____   _____      _____           _____   _____      _____   _____   _____   _____  ||				
    ||_P?__| |_P?__| |_P?__| |_P?__|    |_____|         |_____| |_____|    |_P?__| |_P?__| |_P?__| |_P?__| ||
    |______________________________________________________________________________________________________||
                                          |_____________________________||___________________________|      |
    IIRC they're 14 pin dips so, that's at the very least 16 X's 14x16=224 pins to desolder. Say I find the right chip half way thru, that's still over 100 pins to desolder. There's no way I can possibly remove 100 pins without destroying a solder pad leaving the board in a state that just has more variables leading to non functionality. But the problem could be with a parity chip? Or perhaps the chips physical layout don't map consecutively to the bit pattern (the ? marks). So even if I do all this without screwing up once, it still may not work. On top of all this I'm not 100% sure my reasoning is sound, it *seems* rational. But there is always the possibility I'm a crazy-person with the delusion that I *seem* rational. I mean I have just but a paragraph ago created an ASCII-art diagram of a memory card.


    So I decided to workout the entire schematic of the memory card:

    board(all).jpg

    And then worked out the logic of the card. I've still got all the notes, but it is far from an easy to understand description of the card.

    This was an interesting exercise, but not terribly fruitful. I discovered The parity chips are at the top. Also the chips on the right are read as the first 32-bit word followed by the left chips. On the right set of chips, the one at the bottom left, has its data pin connected to the first pin (component side) of the memory connector. The chip above this is the next pin, and so on. So either this is the LSB or the MSB. On the left side the arrangement is inverted. So the LSB/MSB is the bottom right.

    So then I tried to use the pinout of the 386 to track back to the memory card to workout what was the LSB and the MSB. I got lost at some tri-state chips, and the process started to become very complicated.

    I then looked at alternative ways of desoldering chips, and I ended up using a paint stripper gun. There is another RAM card in existence, so worst case I would order another. In hindsight it would have been much quicker to start with this, but I've at least gained a better understanding of this system. My first plan was to remove a column of RAM, socket them, then test. I was running out of DIP sockets, so next I removed some rows of chips, socketed them, and bingo, now I had an error in a different place. Some switching around and I found the faulty chip.

    Anyway it all seems to be quite happy now. Only thing now is some of the chips in the dip sockets still have some solder on them, so some work loose occasionally.
    Looking for: OMTI SMS Scientific Micro Systems 8610 or 8627 ESDI ISA drive controller, May also be branded Core HC, Please PM me if you want to part with one.

  5. #15

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    This may not be the same, but I found: http://bitsavers.informatik.uni-stut...ence_Jan90.pdf

  6. #16

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    Thanks. But I had already found that manual. It was useful in working out the serial port header.
    Looking for: OMTI SMS Scientific Micro Systems 8610 or 8627 ESDI ISA drive controller, May also be branded Core HC, Please PM me if you want to part with one.

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