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Thread: CPU on Molecular Level

  1. #21
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    Technically speaking, hardware always makes the decisions. The microcode (a type of software) guides the hardware towards the decision, but in the end the logic elements of the hardware do all the work, as sequenced by the microsequencer running the microcode. They operate hand-in-hand. Software can do nothing without the hardware; the hardware is pretty dumb without the software.

    And, at least in older designs, the microcode is hardwired (see the visual6502.org simulation of the 6502 for inspiration). It's only fairly recent that microcode could be updated; I have mixed feelings about microcode that can be updated on-the-fly.
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  2. #22
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    WISC machines seem to appear and disappear regularly. I think I read that some of the VIA X86 CPUs could run custom microcode, but I never investigated it.

  3. #23
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    For what it's worth, the PDP 11/60 can have an option board in its CPU board set for custom microprograms to implement custom instructions. The user control store (UCS) and extended control store (ECS) were definitely interesting tools in the right hands. Now, to get the 11/60 running.....
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  4. #24

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    Quote Originally Posted by ziloo View Post
    I like the word seeing which takes me back to my earlier statement as to
    who/what is making the decision....... hardwire or softwire?


    ziloo
    It is hardware, with the exception that most have what is called patch RAM for instructions that are misbehaving.
    As for order, to make things more confusing, It is possible to have two different AX registers with different values
    executing at slightly different times where only one is the final answer.
    CISC processors, like X86, have the advantage that the know when an I/O operation is coming up and that the processor needs to
    make sure that the I/O gets the right value, when there is out of order executions.
    Today's processors have a lot of ways to optimize execution. These are always a balancing of trade offs. Things like faster DDR
    change how to best use caches. The processors are always being tuned for both execution and today for power consumed.
    There was a company called Transmeta that preprocessed the X86 instructions into a more RISC like instruction to execute from
    the cache. This optimized the execution of a RISC like processor with the more efficient use of memory bandwidth.
    Most cores are more RISC like inside today but more CISC like outside for this reason.
    Dwight

  5. #25

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    I had a class that designed a theoretical CPU from the concept of an inverter and a couple of basic logic gates. The professor was the author and I still rely on basic theory laid out in that book more than 25 years ago.

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  6. #26
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    Thank you all....


    ziloo

  7. #27
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    Modern processors are far more complex than most folks realize. If you're running a reasonably modern Intel CPU, for example, you probably don't even know that there's a little subsystem in there running Minix, that's completely independent of what the main CPU is doing. cf.Intel Management Engine.

    Personally, I prefer the times long ago, when a CPU simply CPU-ed.
    Last edited by Chuck(G); November 28th, 2017 at 07:58 AM.

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