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Thread: Troubleshooting PDP8E Major Register Board M8300

  1. #11
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    I've been trying to test the Register Input Mux. I found that when the machine is idle, EN1 & EN2 are both high, which selects the CPMA register. I monitored PC04 input, pin #6 on chip E30. Then using the switch register I could change the Bit #4 address and this input would show a Zero when the address bit was high and a One when the address bit was low. Then Pin #7, the output of the MUX also showed that it followed. The 74153 chip does not invert the through put. Next I wanted to test the MD04 input to this MUX, but this gave me some problems. In order to test this path I had to worry about timing. I figured that if I would do an Examine, the EN2 line would change from high to low and I could use this a trigger and then monitor MD04 line. I think my problem is using my scope properly. I first checked out the this trigger signal. It starts out high and then drops low for about 250 nSec. Seemed like a nice crisp drop and should make for a good trigger. I left this signal on trace A and then attempted to monitor MD04 on trace B while examining alternating data (0 and 1's). For some reason I could not see any useful data. I then tried MD02 on the same board. This bit works, but I got the same results on the scope. I used MD02, because I didn't have to change the connections on the chip clip, just move the clip to the other chip. So, I'm going to try again, later the afternoon. Mike

  2. #12

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    Quote Originally Posted by Mike_Z View Post
    EN1 & EN2 are both high, which selects the CPMA register...I monitored PC04 input, pin #6 on chip E30...Then Pin #7, the output of the MUX also showed that it followed
    EN1 & EN2 are pins 2 & 14 on E30, the 74153 mux. The 74153 datasheet says that when the A & B inputs (pins 2 & 14) are both high, the input from C3 (pin 3, MA04) is gated to the Y output (pin 7).
    You are seeing the input from C0 (pin 6, PC04) gated to the output. This should happen when EN1 & EN2 (pins 2 & 14) are both low.

    Were you really monitoring the input on pin 3 and not on pin 6?
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  3. #13
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    Am I looking at this wrong? If both EN1 & 2 are both high MA04 is gated, I agree. MA04 is connected to the CPMA Register and address bus. So when I toggle the bit #4 of the address by just turning it one and off I see the changes at this MUX.

    As far as the MD04 line goes, I changed my approach. While doing an examine I watched the MD04 line at the MUX pin #5. There are a couple of transitions. Then I watched the output on pin #7. There is a difference between the good board and the bad, but I'm not sure I fully understand the difference.

    I placed alternating one's and zero's in memory on bit #4. Then Examined thru those memory locations. On the good board I would see a 250 nSec low pulse only when Examining from a high bit to a low bit. On the bad board this pulse occurred for each memory location.

    Then as a second test I changed the data in memory to 8 zero's then 8 one's and then 8 zero's. I watched the bad board. No low pulses for the first 8 zero's then 8 low pulses for the ones and then it continued to low pulse for the last 8 zeros. The good board followed the data pattern. So I suspect the Input Register MUX, but I have to think about why it is doing this before I pull the chip. I hate to heat up the board if I'm not certain this is the problem. Mike

  4. #14
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    Well..... Today I did a little more testing and thinking about the Input Register MUX on bit #4. Something is different between the input/output and the good and bad bits, but could not decipher what it is exactly. So on the chance that it was this chip, a 74153, I replaced it. Bad news is that is not the problem. Good news is, I learned a much better way of replacing chips on a board. In the past I would attempt to wick away the solder and then suck off the rest, but this sometimes damaged the traces. Today I clipped the old chip off the board with a small side cutter, then heated a pad from one side and sucked on the other. This worked great. In more than half of the pads the small IC lead that was left over was sucked out with the solder. The others were easily pulled off later. The pad looked practically brand new. So, since I didn't solve the machines problem, I'm really happy with this new method of pulling a chip off the board. By the way I soldered in a low profile socket. This will allow me to more easily replace the chip if needed or even break the circuit if needed. I suppose the down side is that there is a dry contact now in the circuit which could affect things. We will see.

    I was skeptical that this chip was the problem from the onset. How could a logic chip have any memory. I have seen stuck registers, but never a stuck logic chip that can change. The problem is when bit#4 is a zero it will stay zero while examining memory locations, until a memory location has a one in it. Then all the bit#4's are examined after that, will be a one. Yet a deposit will change it back to a zero. In other words, the memory read of the examine change bit #4 from zero to one, but can not change it back to a zero, yet deposit can. So..... more testing and thinking. Mike

  5. #15
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    I've worked on this some more today, and I have admit, it's a little frustrating. I'd like to layout my troubleshooting logic and should anyone see something wrong with it, speak up.

    First, I have working PDP8E machine. I've run as many of the DEC tests that I can and this machine has passed them all.

    Second, I have a spare M8300 Major Register Card, that when inserted into my good machine exhibits the Bit #4 becoming stuck on a one (high) once a memory one is encountered through repeated examines. Yet a deposit will return the bit to a zero. Since this board is the only change to the working machine, the problem must be on this board.

    Third,
    an EXAMINE will read a memory location onto the MD bus which is brings the memory data to the M8300 board. This data is routed to the Register Input Mux, which is controlled by EN0, 1 & 2. These signals are generated on the M8310 card which is proven good. The Register Input Mux consists of two chips the 74153 and the 8266. The data then goes to the Register In side of the adder, through the Adder output Mux, onto the Major Register Bus and is captured in the MB register. The data is then sent out on the MD bus, off the M8300 board, to be written back to memory.

    a Deposit will read date from the switch register to the data bus which is brings that data to the M8300 board. This data is routed to the Data Control Gate, which is controlled by DATA T & F. These signals are generated on the M8310 card which is proven good. The Data Control Gate consists of a 7487 chip. The data then goes to the Addend In side of the adder, through the Adder output Mux, onto the Major Register Bus and is captured in the MB register. The data is then sent out on the MD bus, off the M8300 board, to be written back to memory.

    I am assuming the an Examine function is failing and the Deposit is working. I make this assumption on the fact that the panel display shows correct lights for the actions taken. The difference between the examine and deposit functions is only slight. Deposit data is switch register data that comes in via the data bus thru the Data Control Gate then to the Adder. Where as the Examine data is memory data brought in via the MD bus, thru the Register Input Mux then the Adder. The rest of the data path for these two function are the same.

    I believe that when the memory data on bit #4 is a one, something in the examine path gets stuck as a one. Then when memory data of zero comes along, it can change it back to a zero and a one is errantly written back to memory. Since the deposit does not do this, I believe that it's path is OK. So the only possible places for the problem is the Register Input Mux (I replaced the 74153 chip today), or the 8266 chip of this Mux, or the Bit #4 Adder the 7483 chip.

    Since this data path is a loop, I do not seem to be able to detect where the problem is. So, I'm scratching my head. I could just replace the other two chips, but I'd like to be sure what is going on and I could be wrong. Mike

  6. #16
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    Mike,

    Just thinking out loud here... The 'easy' way to resolve this issue is to slow the clock down really slow - or (even better) to single-cycle the clock. This would allow you to see what was going on at each part of the clock cycle.

    You can do this on a PDP-11/45 quite easily with a maintenance card - but I don't think this facility exists on an 8/E. I have noticed some unused pins with pull-ups on the timing card - so I will have a look later to see if it is possible to disable the on-board crystal oscillator and to feed an external clock signal in (from - say - a debounced push-button). This may be the only easy option you have of seeing what is going on...

    Dave
    Last edited by daver2; December 8th, 2017 at 08:43 AM.

  7. #17
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    That's a neat idea. I'll look at this also, thanks Mike

  8. #18
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    Quote Originally Posted by Mike_Z View Post
    Since this data path is a loop, I do not seem to be able to detect where the problem is. So, I'm scratching my head. I could just replace the other two chips, but I'd like to be sure what is going on and I could be wrong. Mike
    Are the board revs the same between the M8300 from your good machine and the device under test? Knowing nothing about the PDP-8/E, it may be possible the M8300 and M8310 require a specific set of revisions to work. (spitballing: 8310 works in older machine, but 8300 requires a newer 8310)

    Can you break the loop by bending a pin on the 74153? This might gives some extra insight into the problem, ie grounding the output of the 74153 and looking where the signal goes bad.

    CW

  9. #19
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    Bitly, This is an interesting idea. I'll try can check to see if the boards need to be matched? I do know that my 2nd timing board works fine in the good machine. Always open to ideas that are not mine.

    Dave, I looked at the timing board and there is a spot that I could stop the clock from clicking the shift register, see JPG. ClockCircuit.jpg
    Looks to me that if AB1 is grounded the clock pulses are blocked. So if I made a 25 nSec pulser which would release AB1 from ground for 25 nSec, the next clock pulse would advance the shift register. What do you think? Mike

  10. #20
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    Your schematic is much more readable than mine!

    You are thinking exactly the way I was (now I know what the pin identification is).

    My feeing is that you ground AB1 to stop the clock pulses - but you can generate your own by grounding what looks to be AA1.

    Before doing that, however, can you just check that AA1 and AB1 are not actually connected to anything?

    Dave

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