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Thread: Installing CP/M 3 (Plus?) on a home-built Z80 computer

  1. #381

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    Quote Originally Posted by Alphasite View Post
    I looked in the wboot code in my CP/M Plus BIOS and I don't explicitly clear anything. Doesn't ?rlccp take care of that?

    One thing that might help is to build a non-banked system and test writes.
    Never mind, I was looking at my reload code which moves from a bank instead of re-reading.

    For re-reading I just clear three bytes, ccp$fcb+12 and fcb$nr:

    Code:
    	xor	a		; zero extent
    	ld	(ccp$fcb+15),a
    	ld	hl,0		; start at beginning of file
    	ld	(fcb$nr),hl
    ...
    ccp$fcb:	db	1,'CCP     ','COM',0,0,0,0
    		ds	16
    fcb$nr:		db	0,0,0

  2. #382

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    Quote Originally Posted by durgadas311 View Post
    Just so I have enough information to model this machine, I need some more details:

    1) What does the "MMU active" bit do? The power-on (and I assume RESET) mapping puts ROM at bank 15 at location 0000H (phy addr 3C000H mapped to 0000H), so I wonder what the affect the active bit has.

    2) Is it correct that your monitor is the DMI.ASM code? and it is ORGed at 0000H but loaded into (ROM at) 3C000H?

    3) Is the PIO or CTC actually used right now (do I need to implement them)? I see mention of I2C access via PIO - is that needed (do I need to emulate some I2C devices)?

    4) Do I need to emulate anything on the other end of SIO channel B? Does DMI try to communicate with anything over that serial port?

    5) What is the interrupt daisy-chain ordering for SIO, CTC, and PIO?
    1) MMU active, when low, disables output from the MMU (I actually don't use it, tbh) It's so that you can set up an entire re-map of the Z80's address space in one hit, without doing it 'area by area'. So long as it's low, you can essentially ignore it.

    2) Yes, that's correct. ORG is 0000H, but it's loaded into Bank 15 (3C000h) in the ROM which is mapped to Area 0 at power-on.

    3) No, neither the PIO or CTC are needed for the emulation. The CTC provides a 1Hz clock for the UPTIME command, but nothing will break without the CTC being implemented. The PIO isn't used at all right now - I need to update the readme regarding that as I originally intended to implement an I2C interface with it, but went the way of integrating an ATmega328 instead to do that and more.

    4) You can get by without SIO Port B entirely. It provides communication with the ATmega328, but it's controlled by the Z80 and data only comes down it if the Z80 has requested it. That's basically the clock speed (2/4/8 ASCII char) to manage the baud rate of SIO Port A (you've seen the code for this already in CBIOS64 for CP/M 2.2) but it defaults to 4 MHz if no value is returned anyway. The only other data at the moment is the date and time string for the DATETIME command.

    5) From top to least priority: CTC, PIO, SIO

    EDIT: Should also explain - all the relevant code is in Z80_Minicomp / Z80 Minicomp v2 / Code /
    Last edited by nockieboy; January 13th, 2018 at 03:45 AM.

  3. #383
    Join Date
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    I had a few minutes to look through the latest code.

    I notice that lba0, lba1, lba2 and lba3 are in BIOS BANKED memory (below the DSEG line) but that the specific bank is not set-up when read or write is called. Read and Write calls setLBAaddr (which does a load of maths and stores the value sin lba0..lba3) and then sends the values calculated to the CF registers. It will send the correct data to the CF registers that it calculated - but where did it store the intermediate values in memory of lba0..lba3? If the correct bank (for BIOSBNK) is not in force at the time of the call to setLBAaddr - won't this potentially corrupt four bytes of something?

    I would suggest moving lba0..lba3 before DSEG (i.e. into BIOS common memory - CSEG) and redo the testing.

    I have also noticed a few other coding points - but they are not relevant to the problem in hand so they can wait until this issue is resolved.

    I still don't like using INIR and OTIR to transfer the data without checking DRQ before transferring each byte.

    Dave

  4. #384

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    Quote Originally Posted by daver2 View Post
    I notice that lba0, lba1, lba2 and lba3 are in BIOS BANKED memory (below the DSEG line) but that the specific bank is not set-up when read or write is called. Read and Write calls setLBAaddr (which does a load of maths and stores the value sin lba0..lba3) and then sends the values calculated to the CF registers. It will send the correct data to the CF registers that it calculated - but where did it store the intermediate values in memory of lba0..lba3? If the correct bank (for BIOSBNK) is not in force at the time of the call to setLBAaddr - won't this potentially corrupt four bytes of something?
    NOTE: read/write are always called, in CP/M 3, with bank 0 selected. There should be no problem with lda0-3 being in banked memory, as long as they are used before the switch to dmaBank.

  5. #385

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    It appears that the DMI ROM code requires something "intelligent" be connected to the SIO B port. It tries to get the clock speed from whatever is connected there. Do you have a description of the commands and actions that are executed by that object on SIO B port?

  6. #386

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    Quote Originally Posted by durgadas311 View Post
    It appears that the DMI ROM code requires something "intelligent" be connected to the SIO B port. It tries to get the clock speed from whatever is connected there. Do you have a description of the commands and actions that are executed by that object on SIO B port?
    Yes durgadas311, the ATmega328 is connected to that port. At the moment, you don't need to emulate anything coming back on Port B - it's used to get the system clock speed (provided by the '328 ) so that an appropriate divider can be set for Port A and maintain a constant 125000 baud for the PC terminal, irrespective of the system clock the Z80 is running at. Just make Port B return a string, "%S4#", in response to the %S query from the Z80 to tell the DMI that the board is running at 4MHz. Any other data returned via Port B is to do with the DATETIME command which, if you don't use that command, won't matter and isn't necessary.

  7. #387

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    OK, I was able to get a basic virtual machine running the monitor ROM. I'll get a CP/M image put on the CF card and see if I can boot CP/M 2.2. From there, I'll start trying to reproduce the CP/M 3 problems you are seeing.

  8. #388

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    Any helpful instructions on how to putsys?

  9. #389

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    Quote Originally Posted by durgadas311 View Post
    Any helpful instructions on how to putsys?
    PUTSYS is now part of the DMI as I integrated it into the ROM a few days back. The DMI command, INSTALL, now almost hand-holds you through the installation of CP/M. All you have to do is paste CPM22.HEX and CBIOS64.HEX at the prompts. It should do the rest.

    To install, the following steps are needed in this order:

    In the DMI, type INSTALL
    Load CP/M into memory by pasting the contents of CPM22.HEX into the terminal window
    Load CBIOS into memory by pasting the contents of CBIOS64.HEX (for 64MB Flash drives) or CBIOS128.HEX (for 128MB or larger drives) into the terminal window
    INSTALL will then copy these files onto the CF drive
    Once these steps are complete, CP/M is installed on the disk and can be booted from the DMI with the CPM command. Applications will then need to be installed, starting with the DOWNLOAD.COM program which will allow you to paste files directly into CP/M.

    Next, install DOWNLOAD.COM:

    Type CPM to boot into CP/M then soft/hard-reset the Minicom to return to the DMI (do NOT power off)
    Type BANK 03,00 to map Area 3 of memory to Bank 0 in RAM
    Copy DOWNLOADC100.HEX into memory using RHEX (type RHEX and paste the file contents into the terminal)
    Type CPM to switch back to CP/M
    At the prompt, type SAVE 2 DOWNLOAD.COM to save the program in memory as DOWNLOAD.COM
    Hey presto! You can now copy and paste the Transient Program Packages supplied in the project into the CP/M terminal window.

    If it doesn't work (and it just occurred to me that I haven't actually tested it as far as writing to Sector 0 as it's such a recent addition) then you can do it manually. Type RHEX, paste CPM22.HEX, then type RHEX and paste CBIOS64.HEX, then type RHEX and paste PUTSYS.HEX. Finally, type CALL 5000 and Bob's your uncle.

  10. #390

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    Thanks. Turns out it's pretty easy to load things onto the virtual CF card using "cpmtools", also.

    I'm making good progress, but not getting the same problem as you saw. I'll keep working out the kinks in my simulation.

    FYI, I'm getting this:

    Code:
    CP/M V3.0 Loader
    Copyright (C) 1982, Digital Research
    
     BNKBIOS3 SPR  F400  0C00
     BNKBIOS3 SPR  AC00  1400
     RESBDOS3 SPR  EE00  0600
     BNKBDOS3 SPR  7E00  2E00
     
     59K TPA
    
    MINICOM CP/M Plus BIOS 1.0
    by J.Nock & D.Miller 2017-18
    
    CP/M Plus Copyright 1982 (c) Digital Research
    
    
    CP/M Error On I: Invalid Drive
    BDOS Function = 98 
    CP/M Error On I: Invalid Drive
    BDOS Function = 98 
    ...ad-nausium...

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