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Thread: Installing CP/M 3 (Plus?) on a home-built Z80 computer

  1. #371

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    I was checking this earlier... write cache is (supposedly) disabled. The commands are given in cold boot. I'm assuming they don't get "undone" someplace.

    The CCP FCB is in common memory, in the last BIOS3.ASM source file I see.

    ...however, I have not seen the code that ensures the FCB is "reset" during warm boot. The 4 bytes after the name need to be cleared.

  2. #372

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    Quote Originally Posted by durgadas311 View Post
    I was checking this earlier... write cache is (supposedly) disabled. The commands are given in cold boot. I'm assuming they don't get "undone" someplace.

    The CCP FCB is in common memory, in the last BIOS3.ASM source file I see.

    ...however, I have not seen the code that ensures the FCB is "reset" during warm boot. The 4 bytes after the name need to be cleared.
    Yes, it's being reset here, right at the start of ld_ccp which is called by cold AND warm boots:

    Code:
    ld_ccp:
    	
    	; Zero the EXT byte/s
    	LD	A,0
    	LD	B,4								; Loop iterations (bytes to clear)
    	LD	HL,ccp$fcb+12
    clr_lp:	
    	LD	(HL),A							; Zeros the FCB EXT and other bytes
    	INC	HL
    	DJNZ	clr_lp
    Current BIOS3.ASM: BIOS3.ASM.txt

    EDIT: Yes, I use version control but my project is being held on Bitbucket. (It's private so you'll need to have a Bitbucket account for me to give you access.)

  3. #373

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    Quote Originally Posted by durgadas311 View Post
    I was checking this earlier... write cache is (supposedly) disabled. The commands are given in cold boot. I'm assuming they don't get "undone" someplace.

    The CCP FCB is in common memory, in the last BIOS3.ASM source file I see.

    ...however, I have not seen the code that ensures the FCB is "reset" during warm boot. The 4 bytes after the name need to be cleared.
    I looked in the wboot code in my CP/M Plus BIOS and I don't explicitly clear anything. Doesn't ?rlccp take care of that?

    One thing that might help is to build a non-banked system and test writes.

  4. #374

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    I am "durgadas311" now on bitbucket. Please grant read access. thanks!

    Very strange that ^C does not work but you can return from running programs. Both should be passing through "wboot", I think. Since CCP is a regular program at 0100H just like PIP.COM, etc, the reload of CCP must be working those times. It must have to do with other actions taken for ^C.

  5. #375
    Join Date
    Jun 2012
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    Just 'tossing another idea in here" whilst coding a bit of VHDL...

    You are not using interrupts of any type here are you - this is a purely polled console input/output isn't it?

    Dave

  6. #376

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    Quote Originally Posted by daver2 View Post
    Just 'tossing another idea in here" whilst coding a bit of VHDL...

    You are not using interrupts of any type here are you - this is a purely polled console input/output isn't it?

    Dave
    Interrupts remain disabled in BIOS3 at the moment, Dave. I will need to move away from polled I/O back to interrupt-based at some point for the extra features of my system to work with CP/M 3, but I'm prioritising getting it working at all first.

    Well, saying that, I'm assuming nothing else anywhere is enabling interrupts again. Latest version of BIOS3.ASM is available in a previous post..

    Are you flying off anywhere nice, btw?

  7. #377
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    Edinburgh...

    Sounds nice - but all I will see is an airport, a Premier Inn and the inside of an office!

    Dave

  8. #378

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    Quote Originally Posted by daver2 View Post
    Edinburgh...

    Sounds nice - but all I will see is an airport, a Premier Inn and the inside of an office!

    Dave
    Oh, that takes a bit of the fun out of the mental image I had... I was thinking Hawaii, the Bahamas or California (not Minnesota - too cold at the moment eh, durgadas311? ). All this virtual conferencing equipment these days and you still can't beat being there in person.

  9. #379
    Join Date
    Jun 2012
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    If you're not there you don't know whether they are working on your job or not...

    Many years ago I was in Sydney Australia and a work colleague was in Virginia US. We decided that we had to have monthly face-to-face meetings and it would be unrealistic for one of us to travel to the other's place of work. The best thing for it was for us to meet halfway. Eventually, our boss caught on that halfway between the two was Hawaii!!!

    That was in the bad old days of course...

    Dave

  10. #380

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    Just so I have enough information to model this machine, I need some more details:

    1) What does the "MMU active" bit do? The power-on (and I assume RESET) mapping puts ROM at bank 15 at location 0000H (phy addr 3C000H mapped to 0000H), so I wonder what the affect the active bit has.

    2) Is it correct that your monitor is the DMI.ASM code? and it is ORGed at 0000H but loaded into (ROM at) 3C000H?

    3) Is the PIO or CTC actually used right now (do I need to implement them)? I see mention of I2C access via PIO - is that needed (do I need to emulate some I2C devices)?

    4) Do I need to emulate anything on the other end of SIO channel B? Does DMI try to communicate with anything over that serial port?

    5) What is the interrupt daisy-chain ordering for SIO, CTC, and PIO?

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