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Thread: Qbus Interface Design Collaboration

  1. #1
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    Default Qbus Interface Design Collaboration

    Hello again DECheads,

    I've noticed what seems to be an increasing interest in prototyping hardware for the Qbus. I, for one, am tinkering on a Qbus processor board as is Peter (cbscpe on VCFED). There's also a recent VCFED post by w3llschmidt indicating a need for Qbus design templates. I'm sure there are others as well if we had an open, low cost and proven way to interface with the Qbus through a standard circuit design. So, I propose that it would be good to set up a design collaborative on Github with the following initial guidelines:

    • Make the project Open Source and Open Hardware compliant under a non-restrictive license (suggestions welcome)
    • Standardize on KiCad for schematic and layout as the tool suite is totally open, free, very capable and community supported
    • Write an initial design specification, evolving as the project issues are resolved and ultimately finalized
    • Create layout templates for Dual and Quad Qbus form factors
    • Address the issue of obsolete bus interface logic with a workable compromise using long-term available devices
    • If needed, programmable logic (CPLD or FPGA) designs must be generic and independent of a particular vendor architecture
    • Also, any PLD tools used must be available under a free license for individuals, hobbyists, etc.
    • Take advantage of group buys for circuit boards and components (like we did with the RL Emulator last year)



    Those are my initial thoughts. I'll go ahead a set up a Github project and welcome anyone's contribution.

    -Ken

  2. #2
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    Quote Originally Posted by kenwickvs View Post
    [*]Address the issue of obsolete bus interface logic with a workable compromise using long-term available devices
    Has anyone ever measured signal integrity on the critical signals on a normal 8-slot backplane with integral termination
    using conventional tri-state logic?

    This comes up over and over. Is this even an issue on a system with no bus extension cables?

  3. #3

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    Hi Ken,

    that sounds really good!

    Im new on QBUS and i want to understand how it works. So my first goal is to access the bus an see whats going up there with my Dsview.

    This is where the idea come from:



    http://retrocmp.com/images/stories/j...adapter-01.jpg



    http://svn.so-much-stuff.com/svn/tru...br/dec-con.lbr

  4. #4
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    Quote Originally Posted by w3llschmidt View Post
    Im new on QBUS and i want to understand how it works. So my first goal is to access the bus an see whats going up there with my Dsview.
    I think you mean Unibus.

    QBus is similar but uses multiplexed address and data. The interrupt mechanism is quite a bit different too.

    Bus termination values are also different between the two busses.

  5. #5
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    I created a public repository on Github titled "Qbus-Interface-Design" here:

    https://github.com/kenwick/Qbus-Interface-Design

    Obviously, there's nothing there yet, but I'll take the lead and begin drafting the specification for review/comment by anyone interested.

    -Ken

  6. #6

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    Just for reference purpose.
    Enclosed files from my Q-BUS <-> CTI-Bus ( from Pro 350 ) converter
    If you are interested, I would like to provide the Macro-11 driver software for rt11,
    a test program and a formatting program. Or at http://www.pdp11gy.com/5E.html#5.
    QBUS-CTIBUS-CHIPS.jpg
    Drawing.jpg

  7. #7
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    Hi,

    I think the first thing we need to solve is the level conversion. We need to pay attention to the fact that VIL is 1.1V and VIH is 2.25V. This could be achieved with AC logic (74AC04) running at 3V4. This is close. It will however make the board not power safe, that is if the board has no power it will shorten the bus. For the outputs I suggest N-MOSFET. AO3400 (ZXMN3B14FTA) are fast and high-current and at VGS = 2.5V they have a rdson of only 52mOhm and support up to 4A (we don't need that much of course). Quite a few are then required, but they are cheap (30cents in the quantities we need) So for all signals we have a R(eceive) and a T(ransmit) on the card. This is ok except for BDAL0..15 where it creates issues (aka needs more brainware in the design) when interfacing with bidirectional logic (e.g. Memory). So the FPGA needs to have a decent number of IO (about 100) and must have 3V logic IO. Does that make sense?

    Peter

  8. #8
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    How many lines? And are you talking about just AO3400's for low-side drivers? Eg are all signals open-drain/open-collector?

    What about the reverse direction? Use traditional level translators?

    If 32-mA sink-current is enough, I recommend this parts family:

    http://www.ti.com/lit/ds/symlink/sn74lvc16t245.pdf
    "Good engineers keep thick authoritative books on their shelf. Not for their own reference, but to throw at people who ask stupid questions; hoping a small fragment of knowledge will osmotically transfer with each cranial impact." - Me

  9. #9

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    The big problem that we have had with making an Omnibus interface was having bus driver chips that were much faster then the original chips and caused lots of crosstalk on the bus.
    Member of the Rhode Island Computer Museum
    http://www.ricomputermuseum.org

  10. #10
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    Hi Peter, eeguru, Michael et al,

    For reference in this thread following is the original electrical specification for the Qbus from the "PDP11 Bus Handbook" from 1979.

    Bus Drivers
    Devices driving the 120 ohm LSI-11 bus must have open c·ollector
    outputs and meet the following specifications.
    DC Specifications
    Output low voltage when sinking 70 mA of current: 0.7 V maximum
    Output high leakage current when connected to 3.8 Vdc: 25 uA (even if no power is applied to them, except for BOCOK H and BPOK H)
    These conditions must be met at worst-case supply voltage, temperature, and input signal levels.
    AC Specifications
    Bus driver output pin capacitive load: Not to exceed 10 pF
    Propagation delay: Not to exceed 35 ns
    Skew (difference in propagation time between slowest and fastest gate): Not to exceed 25 ns
    Rise/Fall Times: Transition time from 10% to 90% for positive transition, and from 90% to 10% for negative transition, must be no faster than 10 ns and no slower than 1 ps.

    Bus Receivers
    Devices that receive signals from the 120 ohm LSI-11 bus must
    meet the following requirements.
    DC Specifications
    Input low voltage (maximum): 1.3 V
    Input high voltage (minimum): 1.7 V
    Maximum input current when connected to 3.8 Vdc: 80uA even if no power is applied to them.
    These specifications must be met at worst-case supply voltage, temperature, and output signal conditions.
    AC Specifications
    Bus receiver input pin capacitance load: Not to exceed 10 pF
    Propagation delay: Not to exceed 35 ns
    Skew (difference in propagation time between slowest and fastest gate): Not to exceed 25 ns

    @eeguru I think that there are a total of 44 signal lines in a Q22 backplane (if I counted correctly).

    There are a number of discussions on line regarding the obsolescence of all legacy parts that meet the spec. I agree with Peter that we need to focus on this for our collaborative design. I'm not ready to weigh in with an approach, but I'm working on it. No doubt it will be a compromise.

    Thanks for everyone's input.

    -Ken

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