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Thread: Qbus Interface Design Collaboration

  1. #11
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    Yes there are a total of 44 signals on the Q-Bus, however many are special and will reduce the number of IOs. There are some signals we normally do not drive, but only "consult"

    BDCOKH, BPOKH

    then there are some which are only input

    BDMGI, BIAKI

    and there are some which are only output

    BDMGO, BIAKO

    Also they have to be open collector (drain). Tri-State bus drivers are a very bad idea because it will make the design very complicate and it is electrically not equivalent to the Q-Bus design. You need to be able to de-assert individual signals. Not possible with most Tri-State level converters, but very trivial with open collector. The Q-Bus signals are all preloaded with 3.4V. They represent a Thevenin equivalent of a 3V4 power source with an output resistance of 60 Ohms (each end of the bus is terminated with 120 Ohms). Note that a bus terminated with 120 Ohms and a Thevenin source are dynamically not equivalent. But the Thevenin model gives the reason of the requirement of open collector, its output levels and the minimal current source requirements.

    This rules out all modern and currently available off-the-shelf level converters.

    Using discrete transistors to drive the bus is just more work when soldering the PCB, it does however not use more PCB space, as I assume we will not go smaller than SOIC for the bus drivers. Traditionally many Q-Bus cards used TTL 7438 open collector drivers for output only signals or the DS8641 for bidirectional signals. Which was 4 signals in a PDIP-14 package and they still had enough space to add the "logic" of the board. Actually using discrete transistors makes routing easier. And of course you do not have to populate all transistors if your design is for example only a device without DMA, or is using just one interrupt etc. etc.

    The 7438 are still in production, but those are 5V devices. I don't know if it is a good idea to drive the inputs of a 7438 with FPGA outputs. In theory the output levels of FPGAs with an IO Voltage of 3V3 should be compatible with the inputs of a 7438, perhaps somebody with experience with FPGA interfacing to TTL could shed some light on this subject. The 7438 would have the advantage of meeting the output drive requirements of the Q-Bus.

    Peter

  2. #12
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    Thanks for the info. It scratched my brain itch. You still have to level translate or clip the inputs going the other way. So that's even more chips via buffers, quick switches, etc. My $.02, the family of TI chips I linked above have worked well for just about all mid-80's designs I've thrown them at. They only have 35mA sink capacity. However they could be ganged up in pairs. They come in 2, 8, and 16 line versions. So doubling would give 1, 4, and 8 signal bi directional translations. I'm not familiar with QBUS, but as you said if there are a lot of pin-groups or pins requiring individual control, discretes might be better. Though a 6 or 8 gang buffer with individual tri-states (all inputs grounded) and a quick switch would be easier to solder.

    I wouldn't think there would be any issues with an FPGA driving a 5V part input other than the rise times needed to meet a higher ViL/H might stretch the spec'd propagation times a little.

    Sounds like a cool project. Good luck!
    "Good engineers keep thick authoritative books on their shelf. Not for their own reference, but to throw at people who ask stupid questions; hoping a small fragment of knowledge will osmotically transfer with each cranial impact." - Me

  3. #13
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    It seems that there is no standard parts that meet entirely both driver and receiver specifications as discussed 10-years ago here:
    http://www.brouhaha.com/~eric/retroc...ing/chips.html

    The TI SN7438 is a candidate for the OC drivers if the design has separate drivers and receivers. With input thresholds of 0.8Vil(max) and 2.0 Vih(min) it can be driven with 3.3V FPGAs. The Voh leakage current will not be met. It's available in 14 pin DIP and SO surface mount for about $1.50 US.

    We might want to check out the TI AM26S10C quad transceiver which has OC outputs capable of sinking 100ma. It meets the propagation specs, but it is Schottky and has fast rise and fall times (4ns min/10ns typ). The inputs do not quite meet the spec at 1.75Vil, but it's close and the 2.25V Vih is high. Again, the Voh leakage will not be met. It's available in 16 pin DIP and SO surface mount for about $1.50 US.

    Another transceiver is the SN75138 with OC 100ma sinking outputs. The propagation is OK, but there is no rise/fall spec, but it's not Schottky so it's probably not too fast. The Vih is 1.8V min and Vih is 2.9V (way high). It's available in 16 pin DIP and SO, compatible with the AM26S10C, but more expensive at about $3.00 US.

    So, I think a question to be answered before we can resolve the driver/receiver issues is, for our (hobbyist) requirements, can we relax DEC's Qbus specs? If so, what should they be? I envision the target applications to be single chassis/backplanes rather than clusters of cabinets all cabled together over several meters. Perhaps others have different ideas.

    -Ken

  4. #14
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    A quick thought relating to Al Kossow's post early in this thread, it would be very useful to see some captured scope traces (DAL lines would be best) from a heavily loaded PDP. I don't have one, but some folks on this forum do. Any chance of getting this from someone?
    -Ken

  5. #15

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    Quote Originally Posted by kenwickvs View Post
    We might want to check out the TI AM26S10C quad transceiver which has OC outputs capable of sinking 100ma. It meets the propagation specs, but it is Schottky and has fast rise and fall times (4ns min/10ns typ). The inputs do not quite meet the spec at 1.75Vil, but it's close and the 2.25V Vih is high. Again, the Voh leakage will not be met. It's available in 16 pin DIP and SO surface mount for about $1.50 US.
    -Ken
    I used the AM26S10 to interface an FPGA to the Omnibus.
    Member of the Rhode Island Computer Museum
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  6. #16
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    Quote Originally Posted by m_thompson View Post
    The big problem that we have had with making an Omnibus interface was having bus driver chips that were much faster then the original chips and caused lots of crosstalk on the bus.
    Is the AM26S10 the one you're referring to?

    -Ken

    PS, Don't you have a running PDP with a loaded Qbus @ RICM?

  7. #17

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    Quote Originally Posted by kenwickvs View Post
    Is the AM26S10 the one you're referring to?
    We had problems with 74FCTxx and 74ABTxx parts. 74LSxx and 74ALSxx parts worked OK.
    The AM26S10 worked fine for an Omnibus interface for an FPGA.

    Quote Originally Posted by kenwickvs View Post
    PS, Don't you have a running PDP with a loaded Qbus @ RICM?
    All of the Qbus systems at the RICM are little.
    Last edited by m_thompson; June 16th, 2018 at 04:33 AM.
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  8. #18
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    If you ganged buffers 2x2 the TI SN74LVC16T245, SN74LVC8T245, SN74LVC2T45 parts would meet your specs and save you a FPGA pin for each signal minus a DIR+OE set per signal group. But I'll shut-up now.
    "Good engineers keep thick authoritative books on their shelf. Not for their own reference, but to throw at people who ask stupid questions; hoping a small fragment of knowledge will osmotically transfer with each cranial impact." - Me

  9. #19
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    Bidirectional buffers are in fact only helpful for BDAL0..15. However a level converter with dedicated OE for each side instead of DIR and OE would be easier to use with the Q-Bus. The rest is often better handled using a R(eceive) and a T(ransmit) signal on the board. Especially when you want to have a universal board. As you mention driving a 5V TTL with the output of a 3V3 FPGA only will add to the propagation delay as the VOH of FPGA is really near 3V, sufficient for TTL. And we don't need those extra nanoseconds. So I think I will go for the SN7438 as output buffers. I did not see any datasheet that makes a remark towards the leak current (i.e. when the outputs are high). But I cannot imagine that it is too high. However I have seen that the 74HC4050 would make the ideal input buffer when operated at 3V the input threshold is centered around 1.5V (exactly between the Q-Bus levels 1.3V for Low and 1.7 for High). The good thing is the 74HC4050 have no input clamping diodes towards VCC, so input can go higher than VCC (3V in our case), it can go up to 15V. Now I only need to find a reasonable FPGA. One that has about 100 IO, has 3V IO and comes in a solderable package (no BGA) like TQFP-144. One with on chip configuration storage would be nice.

  10. #20
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    Quote Originally Posted by kenwickvs View Post
    PS, Don't you have a running PDP with a loaded Qbus @ RICM?

    All of the Qbus systems at the RICM are little.
    Oh, that's right, you're in Rhode Island Thanks for the info, Michael.

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