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Thread: Why did 386 motherboards use CLK2 and later motherboards use CLK?

  1. #1

    Default Why did 386 motherboards use CLK2 and later motherboards use CLK?

    I noticed that all my 386 motherboards send CLK2 to the CPU whereas my VLB- and PCI-based socket 3 boards send CLK to the CPU. Why did older motherboards send twice the clock frequency to the CPU, thus requiring the CPU to use an internal PLL to halve the frequency? Why did the motherboard not just use a crystal oscillator at the desired internal CPU clock frequency?

    CLK2 is clearly documented in the SXL2 and DLC databooks.

    2X Clock Input (active high). This input signal is the basic timing reference
    for the TI486SXL series microprocessors. The CLK2 input is internally
    divided by two to generate the internal processor clock. The external CLK2
    is synchronized to a known phase of the internal processor clock by the falling
    edge of the RESET signal. External timing parameters are defined with
    respect to the rising edge of CLK2.

    For the TI486SXL2 microprocessors, the CLK2 input is used internally to
    generate the internal core processor clock and the internal bus interface
    clock. The external CLK2 is synchronized to a known phase of the internal
    processor clock by the falling edge of the RESET signal. External timing
    parameters are defined with respect to the rising edge of CLK2.
    On the Intel486 Family of Microprocessors, Low Power Version Data Sheet - Intel486 SX / Intel487 SX & Intel486 DX, it shows CLK2. Then I opened another datasheet for just the Intel486 DX (not low power) and it shows CLK. This indicates to me that there was some design shift during the time of the Intel 486, in favour of CLK. Does anyone have some insight as to why the motherboard and CPUs were designed like this? When I look at the AMD DX/DX2/DX4/DX5 and Cyrix 5x86, they all use CLK.

  2. #2

    Default

    XT Used CLK3 for what it’s worth

  3. #3

    Default

    Someone can probably answer this better than I can, but you don't need a PLL to divide a frequency, you can do it with flipflops. A PLL is a way to double/tripple/etc a frequency.

    IIRC the ISA/286 bus requires double frequency to keep everything in sync, so any 386 that is synchronous to this (say 16MHz for 8MHz bus) could have used just one 16MHz source. Perhaps the 386 required the same arrangement, requiring a 32MHz source.
    Looking for: OMTI SMS Scientific Micro Systems 8610 or 8627 ESDI ISA drive controller, May also be branded Core HC, Please PM me if you want to part with one.

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