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Thread: TRS80 Model III I/O bus assistance

  1. #11
    Join Date
    Jun 2010
    Location
    Vancouver, BC, Canada
    Posts
    303

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    One thing I noticed reading through the project in the book was how incomplete the breadboard diagram was. Their schematic shows tying most of the flip-flop's input line high but the breadboard diagram only has two or three wires on it.

    From what you said earlier I think you have it covered.

    Seemed really odd for an introductory level book to skim over the details.

  2. #12

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    For anyone who has followed this thread. Happy New Year! BTW

    I just made a cable and connected the breadboard to my model 1 computer and the experiment in the book works perfectly (LED blinks). So there must be something problematic in the model III bus interface?? bad buffer ICs or something that is preventing the out signal from staying alive once the OUT 236,16 command is given ?? not sure, but if anyone has any ideas please advise thank you Mike

  3. #13

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    Quote Originally Posted by mjmalecha View Post
    For anyone who has followed this thread. Happy New Year! BTW

    I just made a cable and connected the breadboard to my model 1 computer and the experiment in the book works perfectly (LED blinks). So there must be something problematic in the model III bus interface?? bad buffer ICs or something that is preventing the out signal from staying alive once the OUT 236,16 command is given ?? not sure, but if anyone has any ideas please advise thank you Mike
    Thanks to this thread, I've also done the same a few weeks ago with a Model I and the experiment in the book worked for me as well. I did not try a Model III with the experiment, but recently I've been programming the the Model III bus as well with an external device under development, from BASIC and Z80 programs. I have not had an issue once OUT 236,16 is given.

    You may have a bad chip in that bus driving logic after all.

  4. #14

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    Thank you, yes that is my fear. It works so easily on the model 1. Plus the address & data bus pins are so stable, each pulsing at a similar speed on the logic probe. but on the model II bus. some of the address/data pins are hard low or hard high & some are pushing incredibly fast & some slow. I don't usually get concerned about that, but directly comparing to the model 1 it is a concern. I will have to get a schematic and see what may be in place to buffer the I/O. I don't think the model 1 has a buffer. It would have to be a buffer IC, correct? else I would have other issues with the Model III? everything works fine on the machine so it has to be "isolated" from the data/address buses. Truly a strange mystery. And Im one that cannot let it be! I can do everything I wanted to do on the model 1. But know I want to know whats wrong with my III. All comments/suggestions/insight welcome. thanks

  5. #15

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    See page 39 of the MIII Service Manual
    https://net.pski.retro.s3.amazonaws....9%28pdf%29.pdf

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