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Thread: I wish to create a new DMA/RAM expansion card for the Tandy 1000 line.

  1. #361
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    I also replied to the YouTube video, although I can't say I have any brilliant insights. This doesn't *feel* like a "fake chip" problem to me, since you'd think for as long as any given chip worked (re: the seeming "infant mortality" problem) it'd behave identically in both computers. It's not a terrible idea to go ahead and buy a chip from a reputable source like Digikey but I'm not optimistic.

    If you've read the whole thread there's still the lingering mystery of why the PCB I sent to @blackepyon has never worked for him, despite the board I built up working in my EX and *also* seemingly working in the HX board @RetroGaming Roundup sent me. (I've only had a brief time to smoke-test it but it did complete several rounds of Check-It's RAM test.) This mystery is one of the reasons why I've been slow-rolling turning my prototype into a "finished" PCB that I feel comfortable putting out there for distribution. Between that and your experience I am left wondering if there's some subtle difference in the PCB design (or something) that renders HXes more susceptible to noise on the bus or... something, than the EX. (The trace routing sucks on my prototype; I particularly wonder if there's a possibility that the MEMW signal might be noisy because the "push-retrace" function in Kicad shoved that trace so it loops in a really ugly fashion around the decoder pins and I didn't catch it. If for some reason the strength of that or some of the other control lines is marginal in the HX... I dunno?)

    On the board you're testing are you using the decode design from post #356, but without the AND installed to control A17? (IE, it's enabling the RAM chip when it's in D0000 as well as the lower 384k?) Blackepyon's issues have given me some sinister theories that perhaps there's some sort of decode shenanigans for the upper memory space in the HX that might cause spurious clashes. (That's *almost* the only thing I can think of that substantially differs between the two machines, the HX's much larger ROM.) I'd be curious if it acted any differently if you lobotomized it down to *just* the 384k decode. Probably won't, but curious.
    Last edited by Eudimorphodon; October 21st, 2019 at 12:52 PM.

  2. #362
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    Quote Originally Posted by rkrenicki View Post
    but is there a particular reason why you aren't buffering the datalines through a 74xx245 on your SRAM card? Both currently freely available designs that I have tried on my HX have no issues, but have the data lines buffered, usually with an ACT245
    I would also second this might not be a bad idea to put one in there, on as short of a leash as possible between the bus datalines and the wires going to the chip. I know it's a really short distance between the one on the motherboard and the expansion header, but the rest of the motherboard peripherals are also "north" of that '245, so if you are getting noise from the data line wiring having the buffer will mean it'll only have the potential to mess with data when the card is actually enabled, not all the time.

  3. #363
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    Yeah, a '245 may clear up that congestion so that it's not erroneously trying to read/write data when the A19 is "on" when it shouldn't be. Since you're working with loose wire, it shouldn't be hard to implement.

    By the way, I've only once had an issue with Digi-Key parts, and that was just because they accidentally sent the wrong chip. I notified them, and they sent out the correct one free of charge.
    My vintage systems: Tandy 1000 HX, Tandy 1100FD, Tandy 1000 RSX, and some random Pentium in a Hewitt Rand chassis...

    Some people keep a classic car in their garage. Some people keep vintage computers. The latter hobby is cheaper, usually takes less space, and is less likely to lead to a fatal accident.

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    Quote Originally Posted by rkrenicki View Post
    @misterblack I had commented on your recent Youtube video in regards to this, and to be honest, I have not read through this entire thread here to see if you have already done this.. but is there a particular reason why you aren't buffering the datalines through a 74xx245 on your SRAM card? Both currently freely available designs that I have tried on my HX have no issues, but have the data lines buffered, usually with an ACT245
    Didn't think it was needed as it goes into the expansion connector and then right into a ACT245 on the motherboard that is sitting within milometers of the connector. It goes CPU -> ACT245 -> Expansion Connector with the only other thing sitting on the bus with the expansion connector another 245 going to the Big Blue and other peripherals. So that section is isolated by two 245s and all right next to each other...
    -- Adrian's Digital Basement

  5. #365
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    Quote Originally Posted by misterblack View Post
    the only other thing sitting on the bus with the expansion connector another 245 going to the Big Blue and other peripherals. So that section is isolated by two 245s and all right next to each other...
    Unfortunately the HX board is multi-layer so I can't really trace it completely by eyeball, but it looks like that '245 that's in front of Big Blue and friends, U44, is chained immediately after U40, while presumably a second set of traces buried inside takes U40's lines to the bus connector. That would still mean that any noise coming in from the bus connector would be present on the segment between the CPU and the rest of the system.

    The Direction signal for U40 appears to be controlled by a "whenever the CPU is reading" line; I'm not sure what DEN* is but I suspect it translates to "Whenever the CPU is the busmaster", so effectively it's just an amplifier. The enable switch for U44 is connected to a PAL that's combining a number of signals that includes IOS and MEMR, so... yeah, essentially the rest of the motherboard electrically looks like it's another card on the bus connector so far as the data lines are concerned. If a card on the expansion bus connector is noisy it could definitely be "heard" when the CPU is talking to anything else. Not saying that's what's going on here, but I think that's the logic behind having the data bus buffered on every card. That way it can only trash the bus when it has the podium.

  6. #366
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    Quote Originally Posted by misterblack View Post
    Didn't think it was needed as it goes into the expansion connector and then right into a ACT245 on the motherboard that is sitting within milometers of the connector. It goes CPU -> ACT245 -> Expansion Connector with the only other thing sitting on the bus with the expansion connector another 245 going to the Big Blue and other peripherals. So that section is isolated by two 245s and all right next to each other...
    I just peeked over the schematics again. You're right, noise before the card shouldn't be a problem. Have you tried tidying up the birds nest, just to rule out crosstalk? You could also try clipping one probe from your oscilloscope to A19 and following it along to the CPU to see where those spike are coming from. Maybe check while you're at it to see if the pulses from ALE and AEN don't coincide with them. I don't think it would be working at all if those were buggered, but you never know.

    I should probably do that on mine as well when I get the chance, just to make sure the A19 spikes aren't a common issue.
    My vintage systems: Tandy 1000 HX, Tandy 1100FD, Tandy 1000 RSX, and some random Pentium in a Hewitt Rand chassis...

    Some people keep a classic car in their garage. Some people keep vintage computers. The latter hobby is cheaper, usually takes less space, and is less likely to lead to a fatal accident.

  7. #367
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    Yeah the spikes are there on all the lines and must come from the 373 latches. I went over everything carefully with the logic analyzer and it should not be any issue though -- those spikes are coming from the multiplexing of the address/data/s lines and happen with the memory isn't selected anyway. And yeah, the system is running the memory cheap and writing the the screen perfectly -- which goes through the two onboard 245s -- so if there was excessive noise on the bus there (From the card) it would cause an issue there.

    I did change around the wiring on the birds nest to no avail.

    I have some real 512k SRAM chips at home (on my PCjr -- I forgot!) I will be testing these chips in the PCjr tonight and trying those known good chips on the HX to see what happens.
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    Quote Originally Posted by blackepyon View Post
    I just peeked over the schematics again. You're right, noise before the card shouldn't be a problem.
    Like I laid out I think the worry is more about noise *from* the card potentially messing with something else, but I'm not entirely convinced that's really the boggle here.

    I'm still puzzled by these mysterious pulses; I kind of wonder if it's worth staring at the timing charts in the manuals and see if some sort of epiphany comes out of it. Because the 8088 has that multiplexed bus I wonder if it's "normal" for address lines north of the '373 latches to experience some kind of glitchyness during that phase of the bus cycle, but for some reason the HX is noisier than the EX? (Could they be using different revisions of that Light Blue master timing chip?) I wouldn't think, though, that if it's *that* the SRAM would care any more than anything else on the bus, it's not going to assert itself until it gets the MEMR/MEMW signals at the proper time.

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    Quote Originally Posted by Eudimorphodon View Post
    I also replied to the YouTube video, although I can't say I have any brilliant insights. This doesn't *feel* like a "fake chip" problem to me, since you'd think for as long as any given chip worked (re: the seeming "infant mortality" problem) it'd behave identically in both computers. It's not a terrible idea to go ahead and buy a chip from a reputable source like Digikey but I'm not optimistic.
    The fact that both chips work in the IBM PC Jr but not in the Tandy machines leads me to believe it is due to the Tandy's clock speed, which is the biggest and most obvious difference between a Jr and an HX/EX. The Chinese chips may be stable at 4.77mhz but unreliable or totally unusable at 7.16mhz.

    This also seems like the simplest explanation. If there is a way to force the Tandy to boot at 4.77mhz this could be easily tested. I have only ever lowered the Tandy clock speed with the hot key, I don't know if there is a jumper you can set to change the default to slow/4.77mhz.

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    I bet they were slower chips that were remarked in order to claim to be be 55ns.. Possibly even from another manufacturer. This happens quite often with common chips like the 68000, they take slower 6 or 8mhz parts, and re-mark them to claim to be 10mhz parts. Quite often the chips will work at that speed just fine, but since they are essentially overclocked.. you can run into stability issues.

    However, I am not entirely convinced that the 245 is not necessary.. In looking at the Lotech schematics a little more, it appears that they are using it to isolate the SRAM from the rest of the bus when the specific ranges of memory are not being addressed. It only drives OE low when the specific address lines are high, and otherwise leaves the 245 in a High-Z state preventing spurious data reaching/coming from the SRAM. You may not be having an issue right now because it is the only thing on the ISA Bus, but if you add another device/function post that on-board 245... I think you may run into essentially "collisions" on the bus.
    Last edited by rkrenicki; October 22nd, 2019 at 11:02 AM.

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