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Thread: PDP-9 at the RICM

  1. #81
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    Quote Originally Posted by jackrubin View Post
    That's great news. How close will Dawson be to the museum? I expect he'll be pretty busy but he should be a great asset.
    He is going to URI for grad school, so just a 15 minute drive away.
    Member of the Rhode Island Computer Museum
    http://www.ricomputermuseum.org

  2. #82
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    Quote Originally Posted by tradde View Post
    Sure wish I lived up that way to be able to help. I'd be glad to work on an 8i. Too bad I don't.
    We have so much equipment that needs to be restored and made demonstrable...
    Member of the Rhode Island Computer Museum
    http://www.ricomputermuseum.org

  3. #83
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    Today was a holiday in RI, so I had some more time to work on the PDP-9.

    I ran MAINDEC-9A D3BB-PB TC02 Basic Exerciser test #11, TC02 Instruction Test to see if the issues we had with the Status Register A write/read pattern test were fixed by swapping the S202 flipchips that make up the register. It behaved better because the first bit that was tested was the ENI (Enable Interrupt) and we had swapped the S202 for that bit. Now Function Register bit #3 was failing. Since we are only using TU55 #0 at this point I swapped the S202 that held the ENI bit for the S202 that held two of the tape drive bits. Now whole register passed the diags. We need to investigate this further. I don't like the idea that certain flipchips will only work in certain slots in the TC02. It is possible that I improved the electrical connection between the flipchips and the backplane by moving them, or the circuits for the tape drive unit number are less loaded than the circuits for the Function Register and Enable Interrupt and two of the S202 flipchips have weak transistors.

    After the register tests, the diag starts testing the basic functions of the TC02. It tests skip instructions, interrupts, status conditions, error conditions, and then moves the tape and tests databreak. It failed at this point where it was looking for a second databreak to happen and it didn't. The MR (Mark Track Read) error light was on, so that might have stopped the tape motion and the second databreak. If there really was a Mark Track error it could be caused by tape head skew because we replaced the TU55 tape head, problems with the tape that I formatted on my PDP-8/e, or more problems in the TC02 controller. I will format another DECtape in PDP-9 format on my PDP-8/e, and we can also try a PDP-10 tape we have that was formatted on a KL10 to eliminate the tape format problem. We can borrow a different TU55 from the PDP-8/I to eliminate the tape head skew problem, and we will continue digging into the TC02 controller to see if something else is broken.

    We are making progress, and eventually we will get it working. Then we can try a modified version of DumpRest to write an ADSS image to a DECtape and see if the PDP-9 will boot and run an OS.
    Member of the Rhode Island Computer Museum
    http://www.ricomputermuseum.org

  4. #84
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    I spent some time today chasing an issue with the TC02 DECtape controller where it would interrupt when it shouldn't, and not interrupt when it should. After an hour of chasing signals around the TC02 and the I/O bus I found that the interrupt was coming from the console serial port because I did not have a current loop terminal connected. Oh well. Now on to the Mark Track decoding error.
    Member of the Rhode Island Computer Museum
    http://www.ricomputermuseum.org

  5. #85
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    We connected the logic analyzer to the TC02 Window Register and found that the Mark Track is being read correctly and the data is shifting through the Window Register correctly. The Window Register is 9 bits, and the Mark Track codes are 6 bits. There are two bits of the previous Mark Track code saved so the TC02 can check for the proper sequence of Mark Track codes. There is a lot of circuitry that decodes the contents of the Window Register, the current state of the TC02, and the current function that the TC02 is executing. If anything isn't correct it sets the Mark Track error. Saturday we will concentrate on the Window Register decoding to insure that all of that complicated logic is working.
    Member of the Rhode Island Computer Museum
    http://www.ricomputermuseum.org

  6. #86
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    PDP-9_TC02_MKTK_ERROR.jpg
    D15: 0->WINDOW
    D14: (100)->C0-2
    D13: C-SYNC
    D12: MK BLK START
    D11: MK DATA
    D10: MK BLK END
    D09: MK END
    D08: MKTK Error

    This shows MK BLK START going active at the beginning of a block, then lots of MK DATA for the block, then MK BLK END at the end of the block, then MKTK going active to indicate a Mark Track decoding error.
    Time to look at all of the inputs to the MKTK flip-flop to see what is triggering the error
    Member of the Rhode Island Computer Museum
    http://www.ricomputermuseum.org

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