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Thread: Connecting logic outputs in parallel

  1. #11

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    One problem with fast rise times is that if there are a lot of loads spread along a wire, the miller feedback can cause a double clock towards the end of the wire. It usually takes a lot of loads. This is usually avoided by placing a small resistor in series with each load. That slows the signal and minimizes the effect of the miller feedback.
    I don't think level or edge has an effect except the case I pointed out where there are a lot of loads.
    Dwight

  2. #12
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    I'm more used to seeing Miller effect issues on high-impedance stuff like CMOS or vacuum tube equipment. I suppose if a lead is long enough on a low-impedance TTL output, it could happen, but I've never seen it.

  3. #13
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    Quote Originally Posted by Chuck(G) View Post
    I still don't quite understand why a power gate or buffer won't be used to accomplish the end. All logic families have them.
    Under my self-imposed regime I can only use the technology that I have in the boards that I salvaged or others that I find in the future and in over a thousand boards there were no power ICs at all, so I have to assume that Honeywell used only transistors for this purpose. The "family" of ICs in those Honeywell boards extends to just seven different IC types with a couple of odd ICs that indicate that there was actually an eighth type which may have been phased out. Although made by regular IC manufacturers such as Texas they appear to be specials made for Honeywell, so not part of any regular production family. My project is about sticking to Honeywell's house style from that era and only using their stock components. I doubt that their technicians would have cheated by paralleling outputs, but I would have back then. If I start using other ICs then I may as well use a Raspberry Pi and save myself a whole lot of work.
    Rob - http://www.honeypi.org.uk
    The Internet is a winch to get your project off the ground ... but always have a parachute handy.

  4. #14
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    I simply didn't understand that you were trying to use old stock exclusively.

    What are the switching speeds on this stuff? Would using a darlington as a driver be considered cheating?

  5. #15
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    Quote Originally Posted by Chuck(G) View Post
    I simply didn't understand that you were trying to use old stock exclusively.

    What are the switching speeds on this stuff? Would using a darlington as a driver be considered cheating?
    I tested the switching speed by chaining six gates in series to get an overall delay that was easy to measure and this test yielded on average 20nS per gate with Honeywell's commonly used 33pF feedback capacitors to control the signal rise time on each gate. In their documentation they refer to this configuration as "slow gated buffer amplifiers" so I assume that they also used the ICs elsewhere with smaller capacitors to run as faster buffer amplifiers. I have seen 22pF used in some of their circuits and in a few places where an output connected directly to an adjacent input on the same PCB the capacitor was omitted entirely. In my PCB designs I have made provision for the feedback capacitors but have not installed any between on board interconnections initially. The normal clock speed of the circuits is 4MHz, so depending on the length of the logic chains I have some leeway for switching delays. Having control over the signal rise times on individual gates is an added dimension to the design of IC logic circuits to which I am not accustomed and I may need to experiment with tweaking the capacitor values on individual circuits to ensure reliable operation.

    Tweaking is the order of the day with this old Honeywell technology. The main magnetic core memory unit, which is Honeywell's original design using transistors throughout, has fifty-two trimming pots to tweak as well as feedback capacitors which have to be changed to set the right signal rise times. Fortunately someone in Switzerland sent me a copy of the original thirty page instruction manual on tuning up a newly built memory unit of this type, so I have Honeywell's set procedure to follow. When it comes to my own IC circuit designs I will just have to see what happens though. Currently I am giving serious thought to the layout of my logic modules on the backplane to get the optimum combination of wire lengths between them, which is also likely to be a factor in choosing those feedback capacitors. So, the answer to your question is that it all depends on many factors.

    Honeywell certainly used transistors in Darlington pair mode for power drivers including some indicator light circuits, such as for the lights on the iconic H200 control panel. I will have to copy that approach for some of my signals, but having to do it for just sixteen unit loads is a nuisance when a normal gate can drive ten. If I can spare the edge connector pins I will just feed the output from two gates to eight loads each separately and not parallel them onto one pin.
    Rob - http://www.honeypi.org.uk
    The Internet is a winch to get your project off the ground ... but always have a parachute handy.

  6. #16
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    That last one would certainly be the way to go--less of a problem electrically speaking.

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