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Thread: OSI 300 Testing

  1. #1
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    Default OSI 300 Testing

    My OSI 300 showed up today! Was surprised at how speedily it got here. The seller really packed it well so no damage or anything.

    I immediately checked it out and powered up with the attached DC adapter. I was able to enter memory into various memory addresses starting at 000 0001 as per the 300 guide, and then read back through them and they look like they're holding. I don't know if that's proof the CPU is alive, but I did proceed further in the manual to try a simple JMP instruction out.

    They say to do the following:

    Assume that a jump command (4C) has been placed at location 01 on page 00. In order to have the jump jump to itself, the second byte of the instruction is 01 while the third byte is 00. (The actual code placed in the machine is translated from hex into binary). Note that on the Model 300 Computer Trainer, only page 00 exists.

    Load the following program into memory:

    Op Code Location Mnemonic
    4C 01 JMP Oper
    01 02 Data
    00 03 Data
    Now, I'm barely remembering doing stuff like this with the ELF, but I'm thinking location 1 of page 0 would be represented in binary as 0000 0001, correct? Thus in terms of the address switches on the 300, you would set the switches, from the leftmost address switch to the right most at 000 0001

    And then to have 4C there, I would go to the 8 data switches, and from left to right, I would do: 0100 1100 ... right?

    So assuming I follow that logic to put in the other bytes, the manual then says you need to put

    the low order memory location, the location within a page, for the beginning of the program at location 7C. This is done by loading memory location 7C with the memory location at which the program will begin. The high order or page is loaded with memory location 7D.
    So that means I need to set the address switches, from left to right, to 111 1100, and set the data switches, from left to right, to 0000 0001 (representing memory location 0001), right? And for 7D, I set the address switches to 111 1101 and the data switches to 0000 0011 (representing address 0003)?

    I then followed the instructions to set RESET to high, set RUN to high, set RESET to low. If I read the manual right, the Data and address LEDs should read 0100 1101 and 000 0011. But I get something different.

    Am I doing something wrong here?

    Here's a pic of the board for reference.

    20190511_165422.jpg

  2. #2
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    Default

    I think I answered my own question. Using what I described above, I powered the machine down and then back up again, and re-entered the data, loaded 00 01 into 7C and 7D (as I understood the requirements for the address switches to be set), and then ran the program again.. and this time it came out with the output that was expected. So I'm thinking that shows the CPU is alive!

    I'm gonna guess I can't see if this one suffers from the ROR bug using this setup. The date code on the chip is 3875 so it's early enough for that...

  3. #3

    Default

    If it's true that only zero page exists, you won't be able to JSR. (Not really a problem but kind of an odd situation for a trainer.)

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