Image Map Image Map
Page 2 of 2 FirstFirst 12
Results 11 to 14 of 14

Thread: "Weird" flip flop .. need some "pointers"

  1. #11


    I have managed to figure out all the connections now, besides some pins on the backplane connectors so far, those I will trace out this evening.

    After that, I'm going to transfer that big mess-o-wires, which the schematic more or less is at the moment, into single pages showing different "modules", labeling the signals consistently and so on.

    I know that the system DOES wait for IO, since if something is missing it will hang indefinitely at the instruction accessing it. That did confuse us, since when we powered the system up it was never ever trying to access the disk, until we connected the screen/keyboard unit, too.

    Also a quite complicated handshake mechanism like that wouldn't make any sense without a waitstate logic?

    But many thanks so far (especially to Dwight for cracking the logic states),


  2. #12


    I'm assuming this was for the Siemens system your working on?

  3. #13


    I'm assuming this was for the Siemens system your working on?
    Yes, it is. And I think I just cracked the last bit of the riddle, how the waitstates are "done".


    This is the actual circuit for the external memory (which is repeated, with only negledgible differences, for the external IO bus). There is another gate, IC75L-A(*) which gates the "ACK" through, if the cycle is "active". This signal (ACKED ~ acknowledged) reaches the wait-state generator, which basically starts a waitstate at every bus cycle, and can cancel it for a plethora of reasons.. sometimes before it has even started.


    So yes, this is all there to do a fully fledged handshake with external components.

    Many thanks again for all the help, I don't think I would have been able to get it all by myself.


    *: If anybody questions my weird numbering scheme .. those are just board coordinates. So, IC75L is at the crossing of "75" and "L". That seemed the easiest way to find them again without a silkscreen.
    Last edited by cerker; August 15th, 2019 at 01:40 PM. Reason: Schematics barely readable

  4. #14


    Quote Originally Posted by Hugo Holden View Post
    One thing with a circuit like this is that it is more difficult to see what it is doing, or can do, with IC's 1A , 2A and 2B drawn as NAND gates because to get a change in output(going low) all inputs need to be high at the same time, and you are thinking in terms of positive logic input signals where "active signals go high".
    If you re-draw the circuit and change those three gates to OR gates, with negated inputs, its much easier to analyse. Also to consider the polarity of the input signals, some of which may be negative active and high most of the time.
    IC1A can be held in a stable state after a pulse by either IC2B or 2A depending if they are enabled or not.
    It is interesting that different training makes one see things differently. When looking at logic diagrams, I don't tend to look a them in terms of positive or negative logic. I only look at them that way when I consider the circuit as a box with input and output. When I analyze a logic circuit, I just remember two rules and don't DeMorgan anything. The rules are for a NAND, any 0 in is a 1 out. For a NOR, and 1 in is a 0 out.
    This is different than when writing or reading RTL where I think about positive or negative logic. I find that in RTL, my most common issue is where I have to combine signal that were thought out in both positive and negative logic. When thinking about ttl logic design, I forget about positive and negative logic and DeMorgan logic back and forth to minimize package complexity and availability.
    I'll admit I don't like constructing state elements from gates and prefer to use something like a D flipflop or a JK, rather than construct such a circuit with gates. In the world of current computer design, designers are not allowed to do such creative state elements that are exposed to simulation tools. As was noted, a logic simulators typically have problems with handling created state elements. Most tools require such circuits to be encapsulated. For complex circuits in current designs, like microprocessors, designs require state element to be accessed by test constructs such as scan or MBIST. This requires that one can not create random state elements with gates.


Posting Permissions

  • You may not post new threads
  • You may not post replies
  • You may not post attachments
  • You may not edit your posts