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Thread: "Weird" flip flop .. need some "pointers"

  1. #1

    Question "Weird" flip flop .. need some "pointers"


    I'm just trying to reverse engineer the CPU board of our "Textsystem" and encounted a "weird flip flop" and can't really wrap my head around it yet. Maybe I have just been following traces for too long the last days.


    They do control the enabling of the system bus drivers, the system has 2 seperate busses for IO and MEMORY. Each of them uses one of those circuits, the enable of the drivers connected to it's output "PAD5" (active low) and "PAD4" is connected to a NAND combination of IOWR/IORD and MEMRD/MEMWR, respectively.

    What I was able to figure out is, that if "PAD4" is low, meaning no active bus access is happening, "PAD5" is always high and therefore inactive. So those other inputs can just inhibit the drivers in some way. Unfortunately they are solely connected to the backplane and therefore I can't yet give them a meaningful "name".

    I have been playing with pen&paper and various logic simulators but I just can't crack it yet.

    Maybe someone just can call out this as an old standard circuit and help me out.


    PS: "PAD2" was optionally pulled to ground by jumpers, but those are not populated on the board, so it can be assumed "high" and therefore irrelevant.

  2. #2


    Further evaluation showed, that there is another RS-Flipflop connected to both times ..


    But it's still weird ...

  3. #3


    It appears to be a variant of a D flip flop.As a rough guess:

    Pad6 = /Q output
    pad3 = /preset
    pad2 = Clock (positive edge triggered)
    pad1 = data input
    pad4 = High enable, or possibly act as a clock input too if pad2 not used and tied high.
    pad 5 = ?

    If this is a unique configuration it might be better tested in a circuit simulator to check its functions. Fundamentally it has the configuration of a flip flop designed to clock input data to its output.
    Last edited by Hugo Holden; August 12th, 2019 at 03:01 AM.

  4. #4


    PAD2 isn't used, it does go to place for a jumper block, which isn't populated though. So its high, making the 4 input NAND basically a 3 input one.

    I tried it in a logic simulator and it doesn't quite work:

    If PAD3 is high it somewhat works like an RS-Flipflop with:

    PAD1 = set
    PAD4 = /reset

    If PAD1 and PAD3 are both high, it just puts out /PAD4.

    It smells of some sort of latch, but I don't get how it works. PAD2 = LOW will immidiately force PAD5 to HIGH and thereby PAD6 to LOW regardless of any stored information.

    I not yet have gathered enough additional schematic to infer what it could be supposed to do..

  5. #5


    Quote Originally Posted by cerker View Post
    It smells of some sort of latch, but I don't get how it works. PAD2 = LOW will immidiately force PAD5 to HIGH and thereby PAD6 to LOW regardless of any stored information.

    I not yet have gathered enough additional schematic to infer what it could be supposed to do..
    Yes it will be easier if you know exactly what it is being fed with. If it were just an S-R latch it would have only required a couple of NAND gates. The circuit appears to be similar to a D flip flop (like a simplified 7474) but where there is no Clear function used.
    Last edited by Hugo Holden; August 12th, 2019 at 01:14 PM.

  6. #6


    It looks like an early/late phase detector. Pad4 arms it. I believe Pad1 is the reference pulse and Pad3 is the signal( I'd have to give it a little more thought ). The reference pulse would be from a oneshot. I've seen similar in Manchester signal decoders. The Manchester decoders were used for data input on signal wire data transmission and things like tape or other magnetic media.

  7. #7


    Here is a truth table
    S is current state number column
    Pv is holds previous state
    Transitions are assumed to be one input bit change at a time

    S : 1 | 3 | 4 || 5 | 6
    0 : 0 | 0 | 0 || 1 | Pv
    1 : 1 | 0 | 0 || 1 | Pv
    2 : 0 | 1 | 0 || 1 | 0
    3 : 1 | 1 | 0 || 1 | 0
    4 : 0 | 0 | 1 || 1 | Pv
    5 : 1 | 0 | 1 || Pv | Pv or if from 7 then 1
    6 : 0 | 1 | 1 || Pv | Pv
    7 : 1 | 1 | 1 || 0 | 1

    State changes only make sense without possible races if one input changes at a time.
    Possible state changes from to states
    0 to 1,2,4
    1 to 0,3,5
    2 to 0,3,6
    3 to 1,2,7
    4 to 0,5,6
    5 to 1,4,7
    6 to 2,4,7
    7 to 3,5,6

    I think I got the tables right.

  8. #8


    One thing with a circuit like this is that it is more difficult to see what it is doing, or can do, with IC's 1A , 2A and 2B drawn as NAND gates because to get a change in output(going low) all inputs need to be high at the same time, and you are thinking in terms of positive logic input signals where "active signals go high".
    If you re-draw the circuit and change those three gates to OR gates, with negated inputs, its much easier to analyse. Also to consider the polarity of the input signals, some of which may be negative active and high most of the time.
    IC1A can be held in a stable state after a pulse by either IC2B or 2A depending if they are enabled or not.

  9. #9


    I figured now the remaining connections in the circuit and it seems to be a bus handshake logic. It's in there twice, once for memory, once for IO. I will show the (reduced) circuit here:


    (It's still a little more complicated in reality, since there are, for example, 2 IORQ lines depending on the state of latched adress bit 3, there is some differentiation between on board and off board circuits and so on.)

    Let's apply the thruth table here:

    We start out in state 3, bus drivers are disabled, IC5A is too, therefore !IORQ is high because of the pullup.
    Then the adress decoders enable the circuit, putting us in state 7. This enables the bus drivers, and after some propagation delay activates !IORQ and puts us further into state 6, which doesn't change anything yet.

    After a while, the hardware activates !IO_ACK. Looking at the truth table, this should us put in state 4 where the bus drivers are already deactivated. That doesn't happen in the simulation and I also don't see it possible by pure thought: As long PAD5 is low, Pin 4 of IC2B is too. So it's output can not go low, which would be necessary to influcence PAD5. Let's just say PAD5 stays low.

    What does happen though, is that Pin3 of IC3A goes low. I have to check if I missed a connection and this creates the "READY" signal for the CPU(!).

    If that is the case, the CPU would now end the cycle and PAD2 goes back low, which puts us into state 1. This disables the bus drivers, thereby !IORQ also goes high because of the pullup and we are in state 2.

    Because of the Request going away, the HW also removes the ACK and we are back in state 3 and ready for the next cycle.

    I have to sleep now, but I will check the "READY" theory tomorrow.

  10. #10


    It looks like I got the states right. The second latch is delayed for the reset, as your flow shows. That is controlling the 3state driver.


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