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Thread: PET 3032 garbage screen problem

  1. #31
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    Those waveforms are OK. It looks like your probes are not compensated correctly to get rid of ringing due to capacitance of probe cable. See https://www.circuitspecialists.com/b...on-adjustment/

    Let's look at F6 (LS157) outputs on sheet 7 http://www.zimmers.net/anonftp/pub/c...N/320349-7.gif with your scope.

    Set the scope to sync on CH1 and connect Channel 1 probe to F6-pin 1 (CLK1). Using CH2 look first at F6-pin 12 (SA0), take a screen shot and then F6-4 (SA1). Try to get three full cycles of waveforms.

    -Dave

  2. #32

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    Quote Originally Posted by dave_m View Post
    Those waveforms are OK. It looks like your probes are not compensated correctly to get rid of ringing due to capacitance of probe cable. See https://www.circuitspecialists.com/b...on-adjustment/

    Let's look at F6 (LS157) outputs on sheet 7 http://www.zimmers.net/anonftp/pub/c...N/320349-7.gif with your scope.

    Set the scope to sync on CH1 and connect Channel 1 probe to F6-pin 1 (CLK1). Using CH2 look first at F6-pin 12 (SA0), take a screen shot and then F6-4 (SA1). Try to get three full cycles of waveforms.

    -Dave
    My probes are compensated correctly.

    CH1 to F6 pin-1 (CLK1), CH2 to F6 pin-12 (SA0)

    UF6_PIN12_SA0.jpg

    CH1 to F6 pin-1 (CLK1), CH2 to F6 pin-4 (SA1)

    UF6_PIN4_SA1.jpg UF6_PIN4_SA1_2.jpg UF6_PIN4_SA1_3.jpg UF6_PIN4_SA1_4.jpg UF6_PIN4_SA1_5.jpg UF6_PIN4_SA1_6.jpg

  3. #33

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    Quote Originally Posted by Fran View Post

    I have doubts if the C3 waves are correct, the output waveforms must be the same as the input waveforms? The output waveforms in B3 are very similar to the input waveforms

    AB0 OUT 6502
    Attachment 55734

    C3 input wabe it is the same

    C3 out
    Attachment 55735
    These waves are not correct, the probe ground was not connected correctly.

    These are the right waves (C3 AB0 IN pin 2 OUT pin 1

    UC3_AB0_IN_OUT.jpg

  4. #34

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    Quote Originally Posted by Fran View Post
    My probes are compensated correctly.

    CH1 to F6 pin-1 (CLK1), CH2 to F6 pin-12 (SA0)

    UF6_PIN12_SA0.jpg

    CH1 to F6 pin-1 (CLK1), CH2 to F6 pin-4 (SA1)

    UF6_PIN4_SA1.jpg UF6_PIN4_SA1_2.jpg UF6_PIN4_SA1_3.jpg UF6_PIN4_SA1_4.jpg UF6_PIN4_SA1_5.jpg UF6_PIN4_SA1_6.jpg
    Hi

    Are these waves correct?

  5. #35

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    Hi
    Dave was complaining about the pictures on post 30. It looks like the ground lead wasn't connected correctly, rather than compensation issues.
    As for the signals, I don't know it they are OK.
    The video RAM is accessed from two different addressing sides. The video circuit addresses the RAM linearly and the processor accesses it to write each byte. One of the two sides looks to be not working correctly. I suspect it is the video side but I do not have a machine to reference. If it is a problem from the CPU side, it might be better to create a ROM to write the sequential addresses. It is harder to analyse the CPU side as it is also running code that is between video accesses.
    Any way, first make sure the video side is doing a sequential address to the video RAM.
    Dwight

  6. #36

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    Dwight, how can I verify that the video side is making a sequential address to the video RAM?
    My electronic knowledges are limited
    I apologise for my ignorance.
    Thanks

  7. #37

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    Looking at the video, the first 16 locations of each block of video RAM are messing up. This alternates as 16 good then 16 bad. The screen is 40 bytes wide but the video RAM is still an array of binary addresses. This would indicate that A4 is not getting to the video RAMs from ether the CPU or the video side. I can see that some characters are getting through partially as I see a + sign showing sometimes. This tells me that the address muxs are most likely working but not getting to all the RAMs. It still might be a mux issue. This sounds like a broken trace or a bad sockets for the video RAM. Check that A4 is getting to all the locations. From the video side it should show a regular toggle. It is harder to see it from the CPU side as it isn't constantly toggling and only updated when the code writes to it.
    Anyway, the key is A4. It is something related to A4.
    Dwight

  8. #38

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    Quote Originally Posted by Fran View Post
    Dwight, how can I verify that the video side is making a sequential address to the video RAM?
    My electronic knowledges are limited
    I apologise for my ignorance.
    Thanks
    The video side will be coming from a counter. It will be a binary count. Look at the schematic. Use the web to identify which chips are counters and which are muxes. The mux will select which side the addressing is coming from ( video counter or CPU ). You can probe the counter with one probe to sync and then compare it to what is getting to the video RAMs. As noted before, A4 is a likely failure. Check each video RAM to make sure it is getting A4. It might be a trace or socket problem.
    It still could be a problem from the CPU side. The socket trick of the 6502 might help to examine A4 from the CPU side. The only issue with it is that it would most likely only access the video RAM for a burst as it goes through the entire 64K memory. Still, that should be useful with your sampling scope.
    To help to see what you are looking for you might look at how A3 and A5 look. A3 will toggle faster and A5 will be slower.
    Don't worry about your knowledge, you'll learn as you go.
    Dwight

  9. #39

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    Lessen in PET video circuit:
    If you look at the display logic schematic page, you will see that video RAM address mux. It switches between the processors address and the address used to scan the video RAM for display. This mux is F3, F5 and F6. These bounce back and forth between the CPUs address and the videos character scan address. The character address is counted by F2, F4 and G6. From the schematic one can see that SA4 comes from BA4 or F4-2 ( QC ) counter. The mux switches back and forth based on CLK1. This makes watching SA4 a little hard. When CLK1 is low, SA4 is driven by the video counter. When CLK1 is high, SA4 is driven by the CPUs address.
    The video counters F2 and F4 keep track of the character currently being scanned on the screen. The video RAM, on the video RAM page, outputs a line of characters to the character ROM to generate each pixel of the screen. It does each column of each character and then increments the character counter to the next character. It has a clever way of keeping track of the character count for the 40 characters because it has to repeat the same characters at each horizontal scan, until all the rows of that character have been displayed. It does this by latching the character counter's initial value, in G3, front the first row of the next characters to be displayed. This way it can reload the character counter with the same character until the entire character rows have been displayed.
    So, the character counter repeats one line of character until all the rows of that line have been displayed.
    What is seems is that there is some issue with SA4 going to the video RAM. This could be a problem with F5, F4 or getting the address to the video RAM. If I were to make a guess, I'd say there was an issue with F5 but that is just a guess, you'll need to probe F5.
    Do you have a separate sync input?
    What would be desired is to sync to F5 pin 14 and watch both pin1 and pin 12. Pin 14 is the counters output.
    Then do the same with pin 13 and pin 12. Pin 13 is from the cpu address. Both of these would be best while looking at the clock and syncing on the first pin.
    You are only interested in what is happening while the CLK1 is high or low and what the CPU address is doing or the counter is doing but the interesting address is SA4, not SA1 or SA0.
    Dwight
    Last edited by Dwight Elvey; September 12th, 2019 at 01:37 PM.

  10. #40
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    Quote Originally Posted by Fran View Post
    Hi

    Are these waves correct?
    I asked for three cycles of the waveforms on the screen to be able to see detail, but you gave me 50. Too hard to see anything. Follow Dwight's instruction as he is hot on the case.

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