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Thread: Designing a 16-bit ROM card

  1. #21

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    When the system is doing 16-bit transfers: do odd addresses ever show up on the ISA bus, or is A0 always low?

  2. #22
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    Quote Originally Posted by maxtherabbit View Post
    When the system is doing 16-bit transfers: do odd addresses ever show up on the ISA bus, or is A0 always low?
    No. Word transfers have to be word aligned - otherwise the BIU or the chipset breaks them apart.
    "Good engineers keep thick authoritative books on their shelf. Not for their own reference, but to throw at people who ask stupid questions; hoping a small fragment of knowledge will osmotically transfer with each cranial impact." - Me

  3. #23

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    clearly not finished, still needs: some bus labeling, decoupling caps, address assignment DIP switch, pull ups for the OC inverters, etc.

    but what's your opinion on the steering logic?

    isa16.pdf

  4. #24

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    my main questions with the logic posted in the previous PDF are revolving around the use of SBHE#

    should I be qualifying my assertion of MEMCS16# with a SBHE# test, or just assert it on a matching address regardless and save 2 gates?

    should I be testing SBHE# in addition to A0 to determine whether an 8-bit read (of the upper byte) is occurring, or assume 8-bit whenever A0 is high and save 2 more gates?

  5. #25
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    Sorry for the delay. I'm at VCF-MW and it's been a long day. Still trying to get my talk ready for tomorrow. I can try and look at this if I have time tomorrow or Sunday. Otherwise will be Tuesday before I'm back in town and things settle down.
    "Good engineers keep thick authoritative books on their shelf. Not for their own reference, but to throw at people who ask stupid questions; hoping a small fragment of knowledge will osmotically transfer with each cranial impact." - Me

  6. #26

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    Quote Originally Posted by eeguru View Post
    Sorry for the delay. I'm at VCF-MW and it's been a long day. Still trying to get my talk ready for tomorrow. I can try and look at this if I have time tomorrow or Sunday. Otherwise will be Tuesday before I'm back in town and things settle down.
    no problem at all, I appreciate any input - no rush

    I went ahead and finished the design, I think it's solid but another set of eyes certainly couldn't hurt
    isa16.zip

  7. #27

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    would still love to get some input on this design before I route out the board and send it to production

  8. #28
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    Sorry for the delay. Busy week. The logic seems to work:

    Code:
                                   A0  SBHE#  D0-7    D8-15   U3D-8  U2B-4
    8-bit read from even address    0    1    Lower    D/C      1      0
    8-bit read from odd address     1    1    Upper    D/C      0      1
    16-bit read from even address   0    0    Lower   Upper     1      0
    Any write                      D/C  D/C   Hi-Z    Hi-Z      1      1
    The only issue I see is when the board is installed in an 8-bit slot, you'll want to have a pull-up on SBHE# to ensure it's state is deterministic.
    "Good engineers keep thick authoritative books on their shelf. Not for their own reference, but to throw at people who ask stupid questions; hoping a small fragment of knowledge will osmotically transfer with each cranial impact." - Me

  9. #29

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    Quote Originally Posted by eeguru View Post
    Sorry for the delay. Busy week. The logic seems to work:

    Code:
                                   A0  SBHE#  D0-7    D8-15   U3D-8  U2B-4
    8-bit read from even address    0    1    Lower    D/C      1      0
    8-bit read from odd address     1    1    Upper    D/C      0      1
    16-bit read from even address   0    0    Lower   Upper     1      0
    Any write                      D/C  D/C   Hi-Z    Hi-Z      1      1
    The only issue I see is when the board is installed in an 8-bit slot, you'll want to have a pull-up on SBHE# to ensure it's state is deterministic.
    excellent, I really appreciate the review

    I'll toss a 30k pull up on SBHE#

  10. #30

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