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Thread: Stack Machine CPU IC, What's Available? If Anything....

  1. #1
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    Default Stack Machine CPU IC, What's Available? If Anything....

    Hi, Lately I have been toying with the idea of building a stack machine computer. This would require a CPU that has more than the rudimentary stack operations of Push, Pop, etc. My research has led to the RTX2000 and RTX2010 CPU's that have been used for spacecraft and other specialized uses. These CPU's are practically impossible to find... at the moment there is one listing on EBAY for an ISA coprocessor card (with an RTX) for about $250. Does anyone have a suggestion for an IC that I might be able to source for tinkering?

    Here is a link to an article about the RTX:

    http://soton.mpeforth.com/flag/jfar/...1/article1.pdf

  2. #2

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    When I started to do this (can't seem to get time to finish anything the past few decades), I just wrote an emulator for a processor of my design. It's not unlike the microcode approach to conventional processors.

  3. #3

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    If it needs to be hardware, you can use a reasonably simple microcontroller (e.g. PIC or AVR) and run the instruction set as an interpreter. Intel has used microcodes in every x86 processor, so this approach has precedent as well. Performance won't be as abysmal as you'd think either.

  4. #4
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    Or write it as an FPGA implementation. Doubtless it will run faster than the original.

    Stack machines were popular for a time as the target for microcomputer compilers. Interpreted execution. I probably should scan the design document that I did for a stack machine backend of a BASIC compiler around 1980. I still have the T-shirt.

  5. #5

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    I believe there are several ( at least two ) stack processor FPGA designs on Github. At $250 for a RTX2000, that is a bargain. The space ready parts are much more than that. I have a setup with a NC4000 but you'll have to wait until I die for that.
    There have been a couple of recent college projects done on these with some actually making silicon as proof of concept.
    They generally run as a fraction, of the power and area, compared to today's ARM and X86 processors. They are typically not as fast to complete a process of about 1/2 to 1/4 the speed per clock but then they are not pipelined( power hungry ) or doing speculative operations either( security ).
    Still, size and power make them look really good for many applications ( really, really good ).
    Dwight

  6. #6

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    The main disadvantage of stack-based CPUs is the fact that every operation has to go through the stack - which is memory. Memory speeds did not increase at the same rate as processing (ALU) speeds and to compensate, they heavily favor burst accessing. That puts stack-based CPUs at a performance disadvantage. But true enough, they are tiny and power efficient (depending on memory).

    Take a look at the ZPU microprocessor, which is a former commercial FPGA design with good compiler support. Also, there is FORTH and corresponding FPGA implementations of it. The ZPU seems to even fit into a CPLD, which might be much closer to what you want as well.

    Good luck.

  7. #7

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    Quote Originally Posted by Svenska View Post
    The main disadvantage of stack-based CPUs is the fact that every operation has to go through the stack - which is memory. Memory speeds did not increase at the same rate as processing (ALU) speeds and to compensate, they heavily favor burst accessing. That puts stack-based CPUs at a performance disadvantage. But true enough, they are tiny and power efficient (depending on memory).
    A well designed cache mechanism would probably help a lot. Many old designs were very memory oriented. The TMS9900 is one design. A good idea when memory is fast compared to processor. Later models added caching.

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    ...not to mention that some stack-based CPUs put the top-most levels of the stack in register memory. I believe that some members of the Burroughs mainframe line did this. I don't know what the ClearPath MPUs do, but it wouldn't surprise me.

  9. #9
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    grrr.. wanted to see if anyone implemented stack caching in hardware Pascal implementations, and all you can find is
    crap about some modern NVIDIA GPU

  10. #10

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    Years ago when I did a FPGA course, I did a 16 register stack cashing. We never got it to work because of timing issues with the Forth engine design I started with.
    As I recall, one of the processors, Chuck M. worked on, most of its instruction as 4 bits with a 16 bit memory. If there were not too many literals needed, it would zip along at 4x memory speed.
    Dwight
    Last edited by Dwight Elvey; September 18th, 2019 at 11:50 AM.

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