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Thread: What were ECC systems like in the 90's?

  1. #11
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    I don't follow--ECC isn't the same as parity. Parity will, for example, allow double-bit errors to pass, but not ECC.

  2. #12
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    Oops. That's a mixup on my part, then! I was under the assumption that ECC involved parity in some capacity.

  3. #13

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    Quote Originally Posted by bear View Post
    so that people could use DIMMs from their PowerMacs.
    Well, yes, it took the same form factor, but near as I could determine even if you used 60ns Power Mac DIMMs, if they weren't parity the ANS would still run them at 70ns. But you may know differently in your infinitely greater experience
    I use my C128 because I am an ornery, stubborn, retro grouch. -- Bob Masse
    Machine room updated for 2019!: http://www.floodgap.com/etc/machines.html

  4. #14
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    Quote Originally Posted by MrArgent View Post
    Oops. That's a mixup on my part, then! I was under the assumption that ECC involved parity in some capacity.
    WikiP has a couple of good pages on error-correcting codes; probably the more relevant:

    https://en.wikipedia.org/wiki/Error_correction_code
    https://en.wikipedia.org/wiki/Burst_...orrecting_code
    https://en.wikipedia.org/wiki/Hamming_code

    I've seen Fire codes (extended Hamming) used on disks, for example. All of this of renewed importance because the MLC (DLC, TLC, QLC) flash devices are particularly prone to errors, which are quietly corrected by firmware.

    The interesting thing about all of this is the evolution. Seymour Cray designed the CDC 6000 supercomputers with no parity or error detection. (The famous "Parity is for farmers" quote). Once wrung out, (main) core was pretty reliable. When the 7600 was designed, it was designed with parity, as the cores were pounded pretty hard and soft errors weren't uncommon. The later STAR used full SECDED and used the 7600 core modules. All this in about the space of 5 years.
    Last edited by Chuck(G); September 25th, 2019 at 03:23 PM.

  5. #15

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    Parity is a simple way to detect a single bit error. It has not ability to do correction of that error. ECC uses a more complicated algorithm that can correct a small burst of errors in a data set. It is better used for serial data than random data but often used for RAM. None of these methods are perfect for all data sets. Particular types of cyclic errors can creep into any data set and not be detected.
    All are better than nothing but not a lot. Systems that fix things without reporting the errors are particularly dangerous.
    Dwight

  6. #16
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    There are "burst" codes, such as Fire codes and then there are ECC block codes (e.g. Chipkill or Hsiao codes) which are not "burst" codes and used for memory.

    I think it's appropriate to mention a rather ancient ECC used on 7 and early 9 track tape drives. That is, the use of a parity bit per frame and a longitudinal parity check for each track. The idea being that the frame parity will indicate what "byte" has an error and the longitudinal bit will indicate which bit within the frame has the error. Reliable for detecting an correcting single-bit errors and provides a basis for guessing the "right" data for multiple-bit errors. The problem, of course, is when multiple bit errors occur (as in a bad spot on the medium) compromise a burst. Those errors are uncorrectable. That's why the big half-inch drives perform an immediate read-after write operation (special head construction) that helps to avoid bad spots on the tape. 9 track 1600 PE and particularly 6250 GCR tapes use a more involved ECC scheme.

  7. #17
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    Lest you think that flash memory is utterly reliable, consider Brian Kim's paper at this year's USENIX conference. Without ECC, today's flash memories would be unworkable.

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