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Thread: Imsai 8080 cannot examine to RAM adress...

  1. #31

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    Hi Jan
    Most strange. The three reads are:

    00000000 should be 00111100
    10010011 should be 00000000
    00001111 should be 11110000 ( assuming you have the four left address switches up and the rest down.
    I get the feeling that you may have your data line swapped but that is not the major issue.
    I'm wondering is we have some data contention. Can we add two more signals. On the CPU card, can we see B9-15 and B9-1 ( or B8-15 and B8-1, which ever is convenient ).
    Dwight

  2. #32

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    No, all 16 switches were down. Now, it´s 1.20 AM o´clock in germany. I´ll make the measurement tomorrow and let you know.

    Like i said, i wrote small programm C3 00 F0 in memory location 0000. After hit reset and three times "single step" and can see the 4 LEDs on the left side. So, adress bus is on F000. When i hit reset and press examine one time, i get the same result. So, hitting examine run the program for 3 steps. So, it runs the small program for three steps from the actual adress..


    Jan

  3. #33

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    If you want to read the values your self, print the screen out and draw lines as follows"
    The data under 6us is the C3 time.
    The data ubder 8us is the low address
    The mark between 9us and 1us it the high address
    Now we are seeing what the processor is reading.
    Dwight

  4. #34

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    Quote Originally Posted by Jan1980 View Post
    No, all 16 switches were down. Now, it´s 1.20 AM o´clock in germany. I´ll make the measurement tomorrow and let you know.

    Like i said, i wrote small programm C3 00 F0 in memory location 0000. After hit reset and three times "single step" and can see the 4 LEDs on the left side. So, adress bus is on F000. When i hit reset and press examine one time, i get the same result. So, hitting examine run the program for 3 steps. So, it runs the small program for three steps from the actual adress..


    Jan
    We've known that it can run programs so that part is expected to work. We just seem to be hung on getting it to read anything from the switches in the Examine sequence. Since we have seen the switches for the high address working in your program, we should be able to see them load on the read of the last address. If you had all the switches down, it is surely strange. What I'm thinking is that for some reason we are not disabling the bus drivers while we are trying to load from the switches in the sequence. It does work for entering data though.
    Dwight

  5. #35

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    Hello.

    I fixed the problem. My Imsai works now !

    At the end, the problem was the U15 7427. The problem was the logic output on Pin 12.




    1000 thanks for your help Dwight ! I learned a lot !


    Jan

  6. #36

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    I hope my wanting to look at the CPU's pins B9-1 and B9-15 helped to lead you in the right direction. I couldn't explain it any other way than buss contention. We were on the right track anyway. We were running out of possibilities.
    Dwight

  7. #37

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    Hey Dwight,

    I am looking at an IMSAI right now, that has what looks like a possible front panel issue as well. I was wondering if you could help me, by taking a look at this video.


  8. #38

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    To understand what might be the problem, you have to first understand how the front panel works.
    First, there is likely nothing wrong with the address bus.
    You have something wrong with the examine next and deposit next.
    Now for how things work when it is working right.
    When you hit reset you are getting a good reset. During the various operations, the processor generates the address, not the front panel. For front panel operations, that is all the processor does, it does nothing else. When you hit "examine", the front panel applies a C3h to the processor, followed by the LSB address switches and then the MSB. This just causes the processor to think it is jumping to the address from the address switches. All it is doing is creating the address for the front panel to use for other operations. This sequence is applied directly to the processor on the 8 wires from the front panel, not through the data bus.
    On the completion of these three processor operations, the processor will output the address to the address bus that is connected to the lights on the front panel. The examine looks to work but you did not show that all the address switches were working or not.

    When you do either "examine next" or "deposit next", the front panel should be putting a NOP or 00H onto the CPUs data input. It is obviously not doing that. It is getting single cycle instruction several of the times that you saw the address increment but that fact that it goes wonky means it is not getting the NOP instruction.
    Also, when the address went wonky, you should have noticed that the status didn't go back to the M1. It took three activation of the switches to get back to the M1. That means that what ever instruction the processor is getting is some type of three cycle instructions.
    I also saw things happening on the data bus a couple times. We should note the address when we see this, this is likely where the RAM really is, maybe not at 0. This is the data on the main data bus. It is only useful when the state is M1.
    Notice also that the examine switch doesn't always work. That is because it was not at the M1 state. That is when it is looking for an instruction. The processor was in the middle of a 3 bus cycle instruction. Some times the "examine next" seems to work those times it was doing a single byte instruction, not necessarily the NOP that the front panel should be sending it.
    I also don't think I saw a successful deposit operation either. ( another symptom to note ).
    What kind of test gear do you have?
    Dwight
    Last edited by Dwight Elvey; December 3rd, 2019 at 09:57 PM.

  9. #39

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    What I see here, is that after binary count of 3 the status lights indicate a Stack operation and jumps to address 6F, and seems to get stuck there, because the system is not looking for an MI. I also noticed, that when he starts with the address in high memory C000 ( I believe this is outside of his actual RAM range) and does Examine Next it counts up normally at least up to C009. So, it looks like the NOPs may be working correctly.
    Where as when he starts at 0000 he only gets to a binary count of 3 and somehow gets a push or pop instruction.

    This is a system, that I am looking to purchase, so I do not have access to it. The first thing that I would do, is put a known good memory card in it, to see if the results were the same. As he was also, unable to make deposit anything into memory.

  10. #40

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    Quote Originally Posted by Novell2NT View Post
    What I see here, is that after binary count of 3 the status lights indicate a Stack operation and jumps to address 6F, and seems to get stuck there, because the system is not looking for an MI. I also noticed, that when he starts with the address in high memory C000 ( I believe this is outside of his actual RAM range) and does Examine Next it counts up normally at least up to C009. So, it looks like the NOPs may be working correctly.
    Where as when he starts at 0000 he only gets to a binary count of 3 and somehow gets a push or pop instruction.

    This is a system, that I am looking to purchase, so I do not have access to it. The first thing that I would do, is put a known good memory card in it, to see if the results were the same. As he was also, unable to make deposit anything into memory.
    There are a lot of instructions that will work as good as a NOP. It just needs to be a single machine cycle operation. Most all of the register to register ALU operations are single cycle. That fact that it looks like it is doing a return instruction or something when it fails clearly means it is not seeing the desired NOP. My guess is that instead of the NOP, it is getting an instruction off the bus.
    It does not stop on M1 sometimes is because it is likely executing something like a 3 cycle 0FFH from the bus. When it does a NOP, it expects it to be a single cycle, so it only does one cycle at a time. That is why, when it goes waky, he has to advance the switch 3 time between seeing the M1.
    All such problems are repairable so, you should get a good price for a broken machine. It is not a problem of bad RAM but I think the RAM card is set to FFFF instead of 0000 as we can see some random data on the data bus after the address goes to the high end.
    That first address it jumped to was CF00.
    Dwight
    Last edited by Dwight Elvey; Yesterday at 05:46 PM.

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