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Thread: Roast my design: 16-bit ISA memory board

  1. #21

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    Quote Originally Posted by ab0tj View Post
    That actually would be helpful. The dimensions for this memory board were just based on some dimensions I found online, not sure how accurate it is. In the short term I have some ISA prototyping boards I can play with.
    ISA edge.zip

  2. #22

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    Quote Originally Posted by ab0tj View Post
    Attachment 57496

    So this may shed some light on it. Looks like MEMCS16# is latched by ALE on the 5170 motherboard. The latched signal goes into a PAL which seems to be doing the data steering stuff. Sooo, it looks like one would have to beat ALE going back low in order to get 16-bit transfers. That would explain why the technical manual says to derive it from a direct decode of the LA lines.
    the forum shrunk the image so much it is illegible, but that would certainly explain the behavior I'm seeing

  3. #23
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    Quote Originally Posted by maxtherabbit View Post
    the forum shrunk the image so much it is illegible, but that would certainly explain the behavior I'm seeing
    http://www.minuszerodegrees.net/manu...0070_SEP85.pdf
    Page 96

  4. #24

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    Quote Originally Posted by ab0tj View Post
    excellent find, that settles that then

    the only remaining question is: on the chipsets that have a second sample point for MEMCS16# is it before or after the command strobes are up?

  5. #25
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    Quote Originally Posted by maxtherabbit View Post
    that settles that then
    Does it? ALE is a clock cycle wide, so on an 8MHz bus that gives 125ns for all the propagation delays and setup times to happen. I wonder if it's possible to reliably beat the clock on that one?

  6. #26

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    Quote Originally Posted by ab0tj View Post
    Does it? ALE is a clock cycle wide, so on an 8MHz bus that gives 125ns for all the propagation delays and setup times to happen. I wonder if it's possible to reliably beat the clock on that one?
    not to discourage additional science, but I did it in 37ns on my card and that wasn't fast enough

    I'm assuming the address isn't actually setup on the ISA bus until a good ways through the latch pulse

  7. #27
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    Quote Originally Posted by maxtherabbit View Post
    not to discourage additional science, but I did it in 37ns on my card and that wasn't fast enough

    I'm assuming the address isn't actually setup on the ISA bus until a good ways through the latch pulse
    That's probably true. Another thing that might be interesting to check out with the logic analyzer.
    At this point I'm leaning towards redesigning the board to use 128K blocks. At least I could backfill 256-640K with 0WS memory and add 128K of UMB

  8. #28
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    Don't worry about 0-wait under 1MB of RAM. 2 cycles vs 3 is 50% faster but you are never going to make a 286 into a speed demon. Most era-correct cards that supported 0-wait only did it for extended memory.
    "Good engineers keep thick authoritative books on their shelf. Not for their own reference, but to throw at people who ask stupid questions; hoping a small fragment of knowledge will osmotically transfer with each cranial impact." - Me

  9. #29
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    Quote Originally Posted by eeguru View Post
    Don't worry about 0-wait under 1MB of RAM. 2 cycles vs 3 is 50% faster but you are never going to make a 286 into a speed demon. Most era-correct cards that supported 0-wait only did it for extended memory.
    Fair enough. At this point I'm more concerned with making some usable UMBs... Given the information that the 5170 latches MEMCS16# on the falling edge of ALE, looks like we are stuck with 128K blocks on this system whether it's 0 or 1 wait state.

  10. #30
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    All the sudden I'm interested in taking a deeper dive into the timing of these signals and how the 5170 (and other chipsets) react to them. I came up with this quick and dirty contraption to do some testing with the logic analyzer. Thoughts?

    ISA16 Test.pdf

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