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Thread: New project - the ROMulator, successor to the PETvet (RAM/ROM replacement plus debug)

  1. #11
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    Quote Originally Posted by gubbish View Post
    The $5 price is just the ICE40 chip itself. It's on a little carrier board which brings the IO out to pin headers and has SPI flash and a couple of regulators and some resistors/caps.
    Is the carrier an off the shelf part? Lattice's breakout board for the chip seems to run about $50...

    Aha! Is it a Gnarly Grey UPDuino? I'd be curious what your thoughts are generally on that as an FPGA learning platform.
    My Retro-computing YouTube Channel (updates... eventually?): Paleozoic PCs

  2. #12
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    It is indeed a UPDuino, the 1.0 version. It's surprisingly inexpensive (about $10 I believe) and was very useful for development. I've seen some grumbling on FPGA forums about the layout of it, and apparently there are some issues with the PLL functionality, but for what I was using it for, it worked great. The documentation for it was pretty sparse and I had to cobble together a few things to fully understand how to program the onboard SPI flash vs programming the fpga directly. The main thing was that the upduino documentation is all for use with the Lattice programming software (ICE studio I believe), but I found it much easier to use the open source toolchain for the ICE40 (yosys/arachne/icestorm). I did end up writing a small programmer application for raspberry pi for programming the SPI flash on the board, and the FPGA reloads from flash upon reset. In general, it is a great board for the price and seems to to the job, but there is a little learning curve to just understand how to get the thing running in the first place. It doesn't have any of the bells and whistles of other dev boards.

    There are, however, a few IO pins available on the chip that are not brought out to the pin headers on the upduino board, so I did another layout to get those extra pins available. Not totally pin compatible with the upduino but either board works with the ROMulator board, with a different pin layout that is controllable in verilog. Hopefully these extra pins will allow VGA output from video ram!

  3. #13
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    Regarding the debug port on the ROMulator,
    currently the debug works over SPI, using a debug application running on a raspberry pi. The FPGA starts out operating as an SPI master, and reads in its own initialization data as well as the PET memory map on reset. Then it switches to an SPI slave, and waits for a debug command to arrive while the system is running. Once the command is received, the 6502 is halted by toggling the RDY line, and the full memory map is sent to the debug application where you can view or modify memory, and if you make changes, can send back the modified memory map. The same connection is used for reprogramming the ROMulator, so you can replace the library of memory maps stored in flash and/or rebuild the FPGA image from verilog if you want to make functional changes. So you can leave it connected and debug a running system
    Incidentally, the available PET memory maps are stored sequentially in the SPI flash, and the FPGA reads one of the maps into its RAM on reset, controlled by the dip switch setting.

  4. #14
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    Another thing to add is that while currently the debug takes place over SPI as described, due to this being an FPGA the same debug pin connection could be used instead as a UART. So if it's useful a serial port debug function could be added, using a 3.3v usb-serial cable.

  5. #15
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    Hi Mike,
    Being one of the early guys to use your PETVet, Please put my name on the list as well for the ROMulator...hopefully it will help me in troubleshooting my PET8032 ( currently at backbench). Thanks

  6. #16
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    Color me interested. I've 2-3 Pets that need repair atm, and this would be just what the doctor ordered!
    ---
    Currently seeking:
    * Roland MPU-401/AT (with daughter card header)
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    I also collect PC and C64 Sierra On-Line software!

  7. #17
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    Interesting project.
    Torfinn

  8. #18

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    im interested in a few as well, will the ICE source code be available? or some framework? i do work on arcade boards that use the 6502 would be great to build some "custom" test boards..

  9. #19
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    Yes, I'll put up the full Verilog source as well as the board schematics. The source is buildable via the open source toolchain for the ice40 fpga, I'll put up some basic tutorials/instructions on building and uploading to the board.
    Quick update on the ROMulator - just got in my fpga boards which will replace the upduino as the fpga carrier board. The tricky part for testing was getting the ICE40 chip soldered on there - it comes in a qfn-48 package which has the large pad on the bottom of the chip as the only ground connection. Tried my hand at some reflow soldering for the first time using solder paste and a cheap reflow oven. Lots of fun, and thankfully after cleaning up a couple of bridges the new boards worked. For ease of manufacturing at the moment I have the voltage regulators and spi flash on a separate little sub-board along with the programming/debug header. This keeps the qfn part alone so it can be reflowed by itself. Hoping to condense these to one and find an assembler which can handle the qfn part and not cost an arm and a leg.
    In any case, will have some working units ready to go within the next week or so, and can start getting them out to those interested.

  10. #20
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    After you get done with this, maybe a improved (and internal) version of the petdisk?



    Please?

    Thanks.
    Later,
    dabone

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