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Thread: getting into programmable logic

  1. #1

    Default getting into programmable logic

    After doing a couple basic PCB designs using KiCad, I was thinking about taking on some more complex projects. Of course I would like to avoid assembling a huge board with a sea of TTL chips (or having to buy all those chips) as was done in the old days. So I started looking into CPLDs. It turns out that these are mostly (but not entirely) considered obsolete now because FPGAs have become less costly, are available with non-volatile config, and are so much more capable. However FPGAs are also overkill for what I want to do. I'm not going to design a whole CPU core as my first project or anything like that. They also tend to come in SMD packages with many pins which I am not prepared to work with.

    CPLDs that are still around include the Atmel/Microchip ATF750, ATF1500, and ATF2500. These can run at 5V and come in PLCC and even DIP packages, perfect for retro stuff. When doing a web search I found a few mentions of the ATF750 but nobody was using them because they aren't supported by many device programmers. ATF1500 on the other hand can do JTAG. As it happens, my old Needham's Electronics EMP-11 is supposed to support both of these devices in the last version of its software (from 2002). So I ordered a handful of both '750 and '1500s. I also bought a 5-piece kit of PLCC-to-DIP adaptors from ebay. Hopefully I should have everything I need to program these chips.

    The ATF750 was described as a 22V10 on steroids. It has 20 flip-flops, which is like 20 data bits. Doesn't sound like much. But, the state of each bit can depend on up to 16 signals, including any of the other "bits" (outputs of the flip-flops) or the state of any of the 12 input-only pins or 10-bidirectional pins. The flip-flops also have clock and reset inputs, and the output pins can invert or go tristate.

    I didn't buy any of the '2500 because they are more expensive than the '1500 and don't appear to be supported on the EMP-11. They are a similar design to the '750 but at a larger scale, ie. 48 flip-flops and more pins. The '1500 has a somewhat different design with OR/XOR gates mixed in and something called "cascade."

    Perhaps one of the downsides of using these chips is the necessity of using WinCUPL to create the logic circuit. It's not nearly as fancy as something like Quartus, and uses its own language rather than Verilog or VHDL. I haven't personally used any of these languages yet so I can't compare them, but I found WinCUPL to be somewhat frustrating at first. It's like a glorified text editor with some command-line tools behind the scenes that do the actual work of compiling the design. It gives very little feedback about what it's doing or what just happened when you clicked that button. A window pops up that says there were X warnings and Y errors, but doesn't say what the warnings and errors are (I think you have to open a separate file to find out). There is a useful simulator included, but it takes a lot of clicking to set it up. There are also a lot of example designs for things like shifters, counters, and even an 8255 parallel port.

    While I'm waiting for ordered parts to arrive, I will try to design something using CUPL.

  2. #2
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    Programming GALs is usually different from programming large CPLDs or FPGAs.

    The languages customarily used are different. FPGA and CPLDs are more the domain of VHDL or Verilog than they are of logic equations or truth tables. Nothing wrong with that, but it's important to appreciate the different approaches.

  3. #3

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    Didn't realize it before, but I should point out that there is an ATF1500, 1502, 1504, and 1508 and there are some important differences between them. Looks like they don't all have JTAG or run at 5V, so don't forget to check the datasheets.

  4. #4

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    Some of my experiences with this:

    WinCupl is buggy. I've had the main window crash a couple of times. So save early and save often. I considered using my own text editor instead but since actually typing in the code is such a small portion of the overall development time maybe it isn't worth bothering. WinSim has a problem where the window doesn't redraw properly sometimes, it needs to be manually resized or manipulated to get it to update. (Another commentator speculated that it happened only on new versions of Windows, but I am running Windows 2000 and it does the same thing.)

    When errors are reported, clicking around in the bottom window that has the compiler messages will open a separate window providing more information on the error. Some of the errors I've had resulted from trying to use a variable name beginning with a number (this is not allowed, gives a cryptic "variable name near..." message), or doing things in the wrong order. Until you give an equation defining the state of an output pin, the compiler is assuming it is an input pin. So you can't set the .oe yet for instance, that has to be done after. The compiler will also throw errors about the heading information, it's giving me flashbacks to being in school again In one case it wouldn't stop giving errors about the heading not matching some other file so I had to close the program and delete everything except the main .PLD source and start over.

    After compiling you can open the .DOC file which contains restatements of all the logic equations and some other information, which hopefully matches what you intended. There are some optimization options pertaining to the compiler. I read that quinne-mcclusky was supposed to be the most comprehensive, therefore I see no reason not to select that since compilation finishes instantly on post-2000 era PCs anyway. I tried compiling a test file with each of the "optimize for polarity" and "demorgan" options toggled on and off and having the former enabled slightly reduced the amount of used resources in the chip. I have a feeling this could be dependent on the design though.

    When targeting the 150x chips, the code should run through the "fitter" which tries to optimally assign resources inside the chip to implement the design. It produces a .FIT file which has a report at the bottom listing how many flip-flops, product terms, pins, etc. were used.

    I have read that a design targetting Altera MAX7000 series and compiled with Quartus can be run through Atmel's POF2JED utility and programmed into an ATF150x. Apparently the chips are that close in function. I installed an old version of Quartus II Web Edition and was going to try running a test file through just to see what the process was like, but a brief search didn't turn up any files appropriate for the MAX7000. I also noticed that the Altera example files had a license statement saying they were only to be used in Altera (now Intel) chips...

    As an example, an address decoder for an ISA card in CUPL might look like this:
    Code:
    pin [2,3,4,5,6,7,8] = [a3..9];
    pin 9 = !ior;
    pin 10 = !iow;
    pin 15 = selectcard;
    field ioaddr = [a3..9];
    selectcard = (ioaddr:240 & ior) or (ioaddr:240 & iow);
    The limiting factor for what you can do with these chips seems to come down to the number of pins or the amount of internal state. For instance, you can't very well run a 20-bit address bus into and out of a 44-pin chip that has 8 pins for power and ground. Chips with 84 and more pins are out there but I'm not keen on routing/soldering those ones...

    But having 64 macrocells means you can only have 8x 8-bit registers, actually less in a realistic scenario. So let's say you'd like to make your own sound chip like the SN76489 used by Sega or the PC-Jr. This chip has 3x 10-bit period registers and 3x 4-bit volume registers. That would be 42 macrocells just to store that information. Each oscillator needs a 10-bit counter to compare with the 10-bit period, now we're up to 72 macrocells. So a 1504 is clearly inadequate, maybe a 1508 with 128 macrocells would be enough.

    I did program something into an ATF750 and test it successfully. The EMP-11 application nearly caused me to freak out however, as a message went by in the log saying that the security bit was TRUE and the device would be "secured" meaning it can't be reprogrammed again. I don't know why it says that as the relevant security options are unchecked in both WinCupl and the EMP-11 options. It turned out to be a false alarm though. In fact there was another message which contradicted it saying that the security fuse would not be activated. I was able to program it a second time after all.

  5. Default

    My PLCC to DIP adaptors finally arrived aaaaaaand I've determined that I can't program any ATF1500 parts using the EMP-11. The 1504AS is in the list of supported devices and when I select it the log shows "adaptor: none" however this is wrong. It does need an adaptor, which is unobtainium and I can't replicate it since I don't know how it is wired. But that just means I'll have to get one of those $5 JTAG adaptors and wire that up instead before I can go ahead with any of the projects I had in mind for this.

    In the meantime I've been doing more reading on CPLDs, FPGAs, and verilog. While the 5V compatibility of the old CPLDs definitely has its uses, it also dates the technology in these chips. I read somewhere that these are made using an 800nm process (just like the Sega Saturn...), which explains their double-digit number of flip-flops compared to thousands or hundreds of thousands in an FPGA made with modern feature sizes. Macrocells, LUTs, logic elements, or just flip-flops all seem to be roughly comparable metrics. There's always a flip-flop with some gates surrounding it to control its operation. In the case of the CPLD it's AND gates and multiplexers, while in the case of a LUT it is some bits of SRAM that yield a certain output value for each possible combination of inputs. Other metrics are also used. A MAX7128 is said to have 2500 "gates" while an ACEX 1K100 with 4992 LUTs has 100,000 gates, leading me to the conclusion that a macrocell/LUT is worth about 20 gates. I think I also saw "LABs" which were blocks of 8 LUTs.

    Verilog looks like it has more abstractions and complexity than CUPL but it's still flexible enough that it can be done in a straight-forward manner, so I could probably handle it. (I don't think I'd like to mess with VHDL.)

    Another difference for FPGAs is the across-the-board choice by the vendors to keep the format of the bitstream a secret, leading to a fairly ugly situation with the development software. One or two series of chips have been reverse engineered and programmed using open source tools. I found a Win32 build of Yosys, but that is only one piece of the puzzle. I couldn't find a Win32 build of arachnepnr or nextpnr, or any build at all for that matter, so I wouldn't be able to go this route.

    I know that Quartus 8.1 and 9.2 definitely run on my computer. The other vendors' software may or may not run, and you have to jump through hoops just to download it. I hate jumping through hoops. So I've been looking at dev boards based on Altera parts. I certainly won't be designing my own PCB for an FPGA since that is too much work for a whimsical experiment, plus they are nearly all BGA parts that have to be machine soldered to a board. Sockets for BGAs exist but they are expensive and also not conducive to hand soldering.

    I am tempted to get the cheap Chinese board with a Cyclone IV on it, but... I actually already have an FPGA board. It's the C-One! I got this ages ago, at a time when the design wasn't finalized. They added an extra RAM card for the C64 core that was in development. I never got the card and this particular board wouldn't do much without it. I forgot about it and it sat in a box until now.

    I found the C-One website that now has alternative cores available and various other necessary files. And since I now have the aforementioned EMP-11 and PLCC-DIP adaptor I can flash a new ROM image and maybe get this board to do something. I already got a boot screen, which is more than I ever had before!

    Quote Originally Posted by bakemono View Post
    quinne-mcclusky was supposed to be the most comprehensive, therefore I see no reason not to select that
    There actually is a reason. Sometimes you have to choose "quick" or the compiler will crash

  6. #6
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    Does Xilinx still have a line of CPLDs? Are any 5V-tolerant? I fell in love with the 9500 series. Good tools, program in Verilog and use JTAG for programming.

  7. #7

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    Quote Originally Posted by Chuck(G) View Post
    Does Xilinx still have a line of CPLDs? Are any 5V-tolerant? I fell in love with the 9500 series. Good tools, program in Verilog and use JTAG for programming.
    yep the XC9500XL series is 5V tolerant and still active production

  8. #8

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    Quote Originally Posted by Chuck(G) View Post
    Does Xilinx still have a line of CPLDs? Are any 5V-tolerant? I fell in love with the 9500 series. Good tools, program in Verilog and use JTAG for programming.
    Xilinx also has the CoolRunner XPLA3 series (XCR3***XL) which I've used and are 3.3V with 5V tolerance. They interface well with 5V logic and have the advantage of very low power requirements compared to the XC9500XL's and most other CPLD's that I've investigated. Xilinx also has the CoolRunner II series (XC2C***) which have even more advantages but are 1.8V core with Vio limited to 3.3V.

  9. #9
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    I've recently decided to try to get into programmable logic myself, and after a very frustrating couple hours I have to ask... does WinCUPL actually work for anyone running Windows 10? Every time I try to run the compile or simulation actions on one of the example .PLDs I get an error message that judging from Google results seems to be a generic Visual Basic runtime error and it bails.
    My Retro-computing YouTube Channel (updates... eventually?): Paleozoic PCs

  10. #10
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    "Works" is a loaded term. I do not know of any Windows 10 specific issues. But WinCUPL has always been crash prone when typing into the built-in editor and terse in error reporting. If you look in the generated files after an error, it will usually have much more detail. But I've had to back out large amount of code on occasion and incrementally add it back to find the origin of a problem. I wish the original author (not Atmel/Microchip) would just open source it and let the community fix the issues with the back-end tools (UI is not worth saving).

    That being said, I don't suppose there are any barriers to anyone (including myself) trying to target some of the open source tools like yosys and nextpnr to a ATF150x or even SPLDs like 16v8s and 22v10s.
    "Good engineers keep thick authoritative books on their shelf. Not for their own reference, but to throw at people who ask stupid questions; hoping a small fragment of knowledge will osmotically transfer with each cranial impact." - Me

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