# Thread: getting into programmable logic

1. Originally Posted by ibmapc
Right, almost. I was the one who talked you into doing the work and then you sold me the eprom programmer you used to program the GAL. Except, it was a GAL16V8 not a 20V10. But hey, maybe I'm being to picky.
No, my wetware is a bit more leaky nowadays...

2. Originally Posted by Chuck(G)
No, my wetware is a bit more leaky nowadays...
That's OK. When you start dripping, the rest of us just try to soak up as much knowledge as we can from your tremendous experience.
When I leak, people just call the guy with the mop. Or, these days, the team of folks in the hazmat suits and garden sprayers full of hospital grade disinfectant

3. Originally Posted by Chuck(G)
Note that I worked out the equations to use a 22V10 as a substitute for a bipolar prom (memory map) on the PC XT. It's buried somewhere on this forum. The neat thing is that most of the pins lined up, with a bit of the 22V10 hanging out of the PROM socket.
My beginner's goal for the GALs I've ordered is to use them as I/O chip selects for a device that sits on an ISA-ish-but-not-quite bus. (Not Tandy Plus bus this time!) I picked the 20v8 and 22v10 chips to experiment with because it looks like I need at least nine input pins to do what I really want. (Decode A3-A9, make all the outputs, six of them if it'll all fit on one chip, depend on the state of AEN, and use an extra input and output pin to invert the RESET signal.)

As an educational exercise I was able to translate equations from that old programming tutorial, which used a piece of software called the "PLAN" logic compiler, into something GALasm will at least compile without errors. That's good enough to convince me it's worth trying to use it as my toolchain. So I guess coming up with my best crack at the equations is my next step, and as far as I'm going to be able to get until my chips and programmer show up in the mail.

4. Originally Posted by Eudimorphodon
I picked the 20v8 and 22v10 chips to experiment with because it looks like I need at least nine input pins to do what I really want.
You can do that with a 16v8 just fine. 16v8 is 16='16 inputs', v='combinatorial + registered logic', 8='8 flip-flops' which means 8 of the 16 pins are I/O rather than just I. The logic diagram within the part's data sheet is eye-opening. Also worth noting, the outputs are not homogeneous with respect to the number of product terms that feed them. So logic that mail fail to synthesize on one output pin may work on another.

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Originally Posted by eeguru
Also worth noting, the outputs are not homogeneous with respect to the number of product terms that feed them. So logic that mail fail to synthesize on one output pin may work on another.
For example, a 22V10 has 44 product terms, but the 10 outputs are limited to 8, 10, 12, 14, 16, 16, 14, 12, 10, and 8 sums of those product terms.

There are some older devices which cannot always be directly replaced by a 22V10 due to the product term limitations of each output. For example a Philips/NXP PLS173/PLUS173 has 32 product terms, and every one of the 10 outputs can be a sum of any of those 32 product terms.

6. Originally Posted by eeguru
You can do that with a 16v8 just fine. 16v8 is 16='16 inputs', v='combinatorial + registered logic', 8='8 flip-flops' which means 8 of the 16 pins are I/O rather than just I. The logic diagram within the part's data sheet is eye-opening. Also worth noting, the outputs are not homogeneous with respect to the number of product terms that feed them. So logic that mail fail to synthesize on one output pin may work on another.
Yeah, I realized after posting that I'd neglected the fact that the "output" pins could also be inputs and that the "special" CLK/OE pins could also be inputs when doing something braindead like a decoder, so even if I wanted nine inputs and 8 outs it would still *just* fit in a 16v8 . But I guess it doesn't really matter, the parts cost effectively the same and the extra inputs might be useful on some other projects. The extra quarter inch of board real estate I can probably spare.

At this point I *think* I've wrapped my head around the minimal syntax I need for the project and have a .PLD that compiles, at least. If anyone's curious what I'm trying to make is essentially a two chip (second chip will be a 74245 buffer) implementation of an XT-CF-Lite that also supplies chip selects for a couple serial ports and a parallel port. (Supplied by a TL16C552A ACE.) I ended up using all the outputs; three are used for selecting the buffer and CS0/CS1 on the 8-bit IDE subset, one is an inverted version of RESET (needed for the CF-lite), and the remaining four lines are chip selects for LPT1 and COM1, COM2, and COM3.

(If I had another output I'd put a COM4 select on there. Since I'm trying to suck up my fear of surface mount anyway I'm thinking of removing the Reset inversion function from the GAL and using one of those 74LVC1G04 single-gate inverters instead. I'm sure I'll have plenty of time to rethink everything before I actually get to apply power to anything.)

7. Originally Posted by eeguru
So logic that mail fail...
Hmm.. I meant to say 'may fail'. I'm either getting old and senile or I'm actually a Westworld Host in the real world and starting to either glitch or experience reveries while typing... Maybe I was the Westworld post master in a previous story arc!

8. Here's another lame newb question, I guess. When using a GAL and you're left with unused pins should those be pulled high (or low) or does it not care if they're left floating?

9. From the datasheet:

Lattice Semiconductor recommends that all unused inputs and tri-stated I/O pins be connected to another active input, VCC,or Ground. Doing this will tend to improve noise immunity and reduce IC Cfor the device.

10. It is also a good idea to wire spare inputs to 10K resistors that are pulled up to Vcc. That way they can used later if needed without cutting traces.

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