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Thread: Did the TRS-80 Model 1 ever insert wait states on memory cycles?

  1. #1

    Default Did the TRS-80 Model 1 ever insert wait states on memory cycles?

    Hi All,

    First post here - I'm hoping someone can help out with a obscure TRS-80 question.

    I'm working on an FPGA implementation of TRS-80 Model 1 and I'm trying to get the timing as close as possible to the original and it just occurred to me that I've been assuming the TRS80 could always satisfy memory read/write cycles without introducing wait states on the Z80. Does anyone know if that's true or not?

    Brad

  2. #2
    Join Date
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    My answer is I don’t *think* so. If you count video as memory The Model III had arbitration circuitry to keep the CPU from accessing video RAM during the active parts of the refresh cycle that can wait the CPU but the Model I didn’t, which is why it has the glitchy display.
    My Retro-computing YouTube Channel (updates... eventually?): Paleozoic PCs

  3. #3

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    Interesting - I did something similar recently. Here's a post on my approach in case you're interested...
    https://www.eevblog.com/forum/vintag...38/#msg2479038

    To your question... The TRS-80 Model 1 did support the wait-states (access to the ~WAIT pin was provided on the expansion connector), but as far as I can tell neither the main board, nor the radio shack expansion board used it. Note however, that IO cycles on the Z80 have an automatic wait-state inserted (not sure whether this matters to your design or not).

    I assume you're aware of this, but just in case your not -- there are pdf of both the "TRS-80 micro computer technical reference handbook" and the "Expansion Interface" manuals available online. Both are great resources for a project like this, containing the original schematics, etc.

    I would look forward to following your progress, please consider posting more about it. Thanks!

  4. #4

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    The WAIT* signal to the Z-80 CPU is not driven by anything in the Model I keyboard or Expansion Interface except a 4.7 Kohm resistor to 5V to make its default state inactive. So no wait states on memory read or write cycles. Of course there is one wait state automatically inserted into input/output cycles though.

  5. #5

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    Excellent - thanks guys.

  6. #6

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    Quote Originally Posted by kizmit99 View Post
    Interesting - I did something similar recently. Here's a post on my approach in case you're interested...
    https://www.eevblog.com/forum/vintag...38/#msg2479038
    That looks like a fun project. Like yourself this is also more about the journey more than the goal. For me this project was about improving my FPGA development skills.

    If you're interested in more info about my project, you can read about it here:

    https://www.toptensoftware.com/blog/tag/big80/

    I also post to twitter about it semi-regularly but can post here too if you think people will be interested.

    Brad

  7. #7

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    Quote Originally Posted by kizmit99 View Post
    Interesting - I did something similar recently. Here's a post on my approach in case you're interested...
    https://www.eevblog.com/forum/vintag...38/#msg2479038
    Cool - looks like it was a fun project. My project is similar in that it's about the journey not the end goal - primarily I'm doing this to improve my FPGA development skills.

    If you're interested in reading more about it I've written quite a bit here:

    https://www.toptensoftware.com/blog/tag/big80/

    I also post semi-regularly about it on Twitter (@toptensoftware) but can also post here if you think others might be interested.

    Brad

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