Image Map Image Map
Page 1 of 2 12 LastLast
Results 1 to 10 of 15

Thread: Dual socket 5 with P266 Tillamook's

  1. #1

    Default Dual socket 5 with P266 Tillamook's

    According to Intel's datasheet, the following features have been eliminated in the low-power embedded Pentium processor with MMX technology: Upgrade, Dual Processing (DP), and Master/Checker functional redundancy.
    ...
    Signals Removed from the Low-Power Embedded Pentium® Processor with MMX™ Technology:

    CPUTYP - CPU Type. This signal is used for dual processing systems.
    PBGNT# - Private Bus Grant. This signal is only used for dual processing systems.
    PBREQ# - Private Bus Request. This signal is used only for dual processing systems.
    PHIT# - Private Hit. This signal is only used for dual processing systems.
    PHITM# - Private Modified Hit. This signal is only used for dual processing systems.


    Sounds like the Tillamook's don't support dual processing. Is there any hack which can be done to these CPUs to get both of them working properly in an SMP environment? Alternately, is there any motherboard which has a workaround to get them working nicely together?

  2. #2
    Join Date
    May 2009
    Location
    Connecticut
    Posts
    4,635
    Blog Entries
    1

    Default

    Do you have a MMO to Socket 5 adapter? I thought Tillamook was only available in a special packaging instead of a desktop socket. The whole issue is rather moot if the chip can't be installed on the motherboard.

  3. #3
    Join Date
    May 2011
    Location
    Outer Mongolia
    Posts
    2,055

    Default

    Those signals listed as absent on those CPUs are basically the entirety of the arbitration signals used for multiple CPU support. If this is accurate there's no way they could ever be used in a standard Intel MPS-compliant motherboard, period. There were non-MPS/SMP multiple CPU machines built, I guess, using proprietary architectures, but I certainly can't think of one that used those particular CPUs.
    My Retro-computing YouTube Channel (updates... eventually?): Paleozoic PCs

  4. #4

    Default

    For socket 5, yes they would need to be placed in a split-rail VRM interposer module, e.g. those from Evergreen, Kingston, etc.

    The Tillamook did come in a PGA varient that works on some desktop boards. http://chipdb.org/img-intel-pentium-...sl2z4-1284.htm I have two such motherboards which work with them. The trick seems to be that ADS# needs to be bridged to ADSC# to get them working. Another bridge for 4x is also sometimes needed.

    I seem to recal that early dual CPU systems, such as 486 and Pentium had some on-motherboard or on-CPU-card controllers to handle the arbitration. I think they were made by Compaq. Was wondering if anyone has been able to get 266 MHz Tillamook's going in these, as it seems Tillamook's don't have built-in SMP support?

  5. #5
    Join Date
    May 2011
    Location
    Outer Mongolia
    Posts
    2,055

    Default

    There was the original Compaq SystemPro that supported a second 386 or 486 CPU card using a proprietary NUMA architecture that was partially supported by one version of SCO Unix and the first version of Window NT, and that’s pretty much it. The SystemPro XL which only allowed 486 CPUs used the standard Intel MPS arrangement.
    My Retro-computing YouTube Channel (updates... eventually?): Paleozoic PCs

  6. #6
    Join Date
    May 2009
    Location
    Connecticut
    Posts
    4,635
    Blog Entries
    1

    Default

    Besides the 1990 era proprietary connections, there were the mesh Pentium-M concepts taking non-SMP processors into the world of massively parallel computing. I haven't heard of anyone trying something similar with Tillamook. Doesn't mean that one of the interposers didn't include dual CPU support though I doubt the value of it. Tillamook doesn't save much power relative to the Pentium III to counterbalance much lower performance and Tillamook's very high cost.

  7. #7
    Join Date
    May 2011
    Location
    Outer Mongolia
    Posts
    2,055

    Default

    Quote Originally Posted by krebizfan View Post
    Besides the 1990 era proprietary connections, there were the mesh Pentium-M concepts taking non-SMP processors into the world of massively parallel computing.
    Technically speaking most mainframe computers with thousands of CPUs are built up from clusters of smaller CPUs (often off-the-shelf Intel Xeon-family chips) that are tied together using what essentially amounts to a very fast networking backbone with DMA support; classic UMA SMP usually tops out somewhere around 32-64 cores. There's actually quite a large gray area between tightly-coupled SMP and what most people would call "Clusters". NUMA architectures have filtered down to the desktop with the invention of multi-core CPUs; when you have a dual-socket Xeon or Opteron it's technically a very *tight* cluster that can be treated as if it was pure SMP because the CPUs have signals to ensure cache coherency between the on-die L2 caches serving each silicon die's cores, but it's preferable if the OS knows it's actually multi-socket because it can schedule tasks to avoid the relatively large hit that comes when a cache needs to be updated across the bus. Once you move beyond ccNUMA then you have technically completely crossed the line into "cluster" territory even if the OS presents the computer as running a "single image" because tasks can no longer arbitrarily execute on any CPU core transparently, they *have* to be scheduled according to processor domains.

    For transparent SMP with CPUs that have any kind of onboard writeback cache you at minimum need some signals available to know when the cache contents are "dirty". If you lack those then, sure, you can still make a "cluster" out of it, but you'll need to write your OS accordingly. A relatively well-known 90's vintage example is the BeBox; the 603 CPUs used in that machine don't automatically generate a signal to tell other CPUs to flush their instruction caches so it required software hacks to work around it. You could certainly build a BeBox-like computer out of something like a Tillamook CPU, but considering by the time it came out Intel had multiple better SMP options (that weren't more expensive) I don't know why anyone would have ever done it.
    My Retro-computing YouTube Channel (updates... eventually?): Paleozoic PCs

  8. #8

    Default

    Interesting information. I remember those beowulf clusters being somewhat popular among some enthusiasts in the 90's.

    I cannot recall the name of the system, but there was a system which had two CPU risers cards with a lot of other logic onboard. At the low end, it came with dual 486 CPUs, but at the higher end, I'm pretty sure P100's were available. It's such a system that I think the Tillamook's might work in.

  9. #9
    Join Date
    May 2009
    Location
    Connecticut
    Posts
    4,635
    Blog Entries
    1

    Default

    Quote Originally Posted by feipoa View Post
    Interesting information. I remember those beowulf clusters being somewhat popular among some enthusiasts in the 90's.

    I cannot recall the name of the system, but there was a system which had two CPU risers cards with a lot of other logic onboard. At the low end, it came with dual 486 CPUs, but at the higher end, I'm pretty sure P100's were available. It's such a system that I think the Tillamook's might work in.
    The multiple CPUs on cards was a design concept from ALR. A lot of support logic was needed and the price was very high. It did get a bit extreme; http://www.cpushack.com/2019/01/16/p...ware-and-bios/ shows a design using 6 Pentium Pro chips (up from the specified maximum of 4). ALR got purchased by Gateway not long after the Pentium Pro design and moved to more affordable yet still high end server designs.

  10. #10
    Join Date
    May 2011
    Location
    Outer Mongolia
    Posts
    2,055

    Default

    IBM made a hex-CPU Pentium machine called the Server 720 that had only one CPU per card. (So you can imagine just how huge that thing was.) However, the fact that machines like this existed that broke the rules for Intel's specified "maximum number of CPUs" doesn't mean that they'll work with CPUs that lack the cache coherency signals required by the Intel MP specification. Intel's maximum numbers refer to "glueless" SMP implementations, IE, that's how many CPUs that can essentially just be slapped onto a motherboard that has little more than a second CPU socket basically wired in parallel to the first one(*) and go to town. With external circuitry you can scale horizontally significantly beyond the built-in dual/quad limits. Here's a copy of the Intel MP specification paper; if you can guarantee transparent cache coherency the ultimate limit is some fraction of an 8-bit number. The specification even supports CPUs of different types and capabilities, within reason; mixing 486 and Pentium CPUs might be pushing it but doesn't look strictly impossible...

    (* Obviously that's an oversimplification.)

    But, anyway, the point is that the fact that systems existed that used a bunch of glue to stuff an "abnormal" number of CPUs into a system is not evidence that those systems didn't require the MP signals from the individual CPUs to be present; it's *very* likely that most of them used them as part of their cache coherency system.
    My Retro-computing YouTube Channel (updates... eventually?): Paleozoic PCs

Bookmarks

Posting Permissions

  • You may not post new threads
  • You may not post replies
  • You may not post attachments
  • You may not edit your posts
  •