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Thread: DATBO and DATBI protocol detail

  1. #1

    Default DATBO and DATBI protocol detail

    Hello,

    I'm making Q-bus memory with start address and end address selectors using CPLD and 32Mbit SRAM.
    Currently, it supports only DATI, DATO and DATIOB. The post-fit random test shows no serious hazard.
    (Problem is that the code is very dirty asynchronous and synchronous mixture.)

    My first goal is LSI-11/23 + MXV11-A and 48kW system (16kW in MXV11-A + 32kW my own board).
    Then, I'll try larger system.

    Also, I want to implement DATBO and DATBI but I couldn't find detail documentation of these protocols.
    I found the bus cycle in the user's guide of MSV11-Q but there is no timing chart.
    Also, I guess the memory device increments the address because they are "block mode".

    Do you know any documentation on detail of DATBO and DATBI protocol?

    coredump

  2. #2
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    Have you seen these documents?

    EL-00160-00-0_A_DEC_STD_160_LSI-11_Bus_Specification_Sep91.pdf
    PDP11_BusHandbook1979.pdf

  3. #3
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    The following document, although it is for the KA680 CPU Module used in a VAX4000-500, has all the required information http://www.bitsavers.org/pdf/dec/vax...80_TechMan.pdf. Appendix F has a full Q22-bus specification. And the quality of the scan is very good. It also has an engineering drawing of the Q-Bus card dimensions.

    By the way which 32Mbit SRAM are you using? For my Q-Bus Memory I was using 16Mbit SRAM chips because I did not find a source for 32Mbit SRAMs that can be operated at 5V. I still did not find the time to implement Block Mode DMA, but have my hopes up to do so in the future. The hardware is Block Mode Ready but the CPLD needs some enhancements.

    Peter
    For more information about my projects see https://www.5volts.ch

  4. #4

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    Hi, cruff and Peter,

    Thanks a lot for documents. I'll try to implment DATBI and DATBO.

    Quote Originally Posted by cbscpe View Post
    By the way which 32Mbit SRAM are you using?
    I'm using 3.3V SRAM and XC9500XL, 5V tolerant 3.3V I/O CPLD. Peter's design of the input logic seems to be friendly to 3.3V I/O.

    Because of my small experience of HDL, I connected all SRAM singnals, including the data bus to CPLD. So, I can use very simple SRAM model and I don't take care of SRAM timing.
    But this idea gave terrible timing problems.

    Anyway, I still have issue on start address and end address selectors but I have not yet identified the reason. That is, I don't know whether it is RTL designe issue or test bench issue.

    coredump

  5. #5

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    DEC documents show block mode transfere must not cross 16-word boundaries.

    Should a master or a slave check the boundary?

    DATI/DATO/DATIO/DATBI/DATBO tests pass random post-fit simulation but I have not yet implemented the 16-word boundary check. Currently, my HDL code accepts any block mode transfers.

    coredump

  6. #6
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    Quote Originally Posted by coredump View Post
    DEC documents show block mode transfere must not cross 16-word boundaries.

    Should a master or a slave check the boundary?

    DATI/DATO/DATIO/DATBI/DATBO tests pass random post-fit simulation but I have not yet implemented the 16-word boundary check. Currently, my HDL code accepts any block mode transfers.

    coredump
    Normally in digital design only the lower bits of the address are connected a counter, in this case a 4 bit counter. The upper bits are latched at the beginning of the transfer and held constant throughout. This saves area, and allows the auto-indexer to run much faster (only a 4 bit counter instead of a 16/18 bit counter).

    If a transfer crosses a 16 word boundary, the memory before the beginning of the destination gets overwritten. This is avoided by the master hardware, or more commonly by the software that is setting up the transfer.

    CW

  7. #7
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    Quote Originally Posted by Bitly View Post
    Normally in digital design only the lower bits of the address are connected a counter, in this case a 4 bit counter. The upper bits are latched at the beginning of the transfer and held constant throughout. This saves area, and allows the auto-indexer to run much faster (only a 4 bit counter instead of a 16/18 bit counter).

    If a transfer crosses a 16 word boundary, the memory before the beginning of the destination gets overwritten. This is avoided by the master hardware, or more commonly by the software that is setting up the transfer.

    CW
    Block mode is a handshaking process of Master and Slave. There is no boundary the master must respect. The master requests DMA and if the Memory supports Block Mode DMA it signals via BREF and in case of DATBI also via BWTBT that it can perform another word transfer after this transfer. In other words with each word transfer the memory signals if it is ready for the next word. If the memory signals that it does not support another word the Master must finish the DMA cycle after the memory has de-asserted BRPLY. Now as Bitly said, the memory does normally not implement a full address incrementer but only has an incrementer for a limited number of address bits, typically the address bits A1..4. So depending of the start of the DMA cycle, the memory can go for another 0..15 words. The memory must signal that it cannot support a further transfer when the counter has reached it's top value. It could of course also have a larger or smaller counter. However there is also a rule a master must observe. First if it monitors BDMR,and after 7 transfer there is no other device requesting DMA the master can continue and transfer a total of up to 16 words. If it does not monitor BDMR then it is only allowed to transfer a maximum of 8 transfers. Typically when transferring a large block of data, the first DMA might only transfer a few words until the address counter of the memory reaches top. But then the next transfer will start at bottom of the counter and with a 4 bit counter DMA could deplay the full maximum in this and subsequent requests, most likely up to the second last one.

    Peter
    For more information about my projects see https://www.5volts.ch

  8. #8

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    I understand why the block mode transfer cannot cross 16-word boundaries.

    I'll compare timings of (1) 22-bit counter without 16-word boundary limitation and (2) 4-bit counter with 16-word boundary limitation.

    By the way, the timing between RDINH/RDOUTH and TRPLY meets the specification in the LSI-11 BUS SPEC document but violates that in the KA680 CPU module technical manual. The post-fit simulation shows the interval is about 13 ns.
    I wrote the simple HDL code, but post-fit simulation still gave 13 ns interval, being longer than 8 ns. Maybe it is the limitation of CPLD speed.

  9. #9
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    Quote Originally Posted by coredump View Post
    I understand why the block mode transfer cannot cross 16-word boundaries.

    I'll compare timings of (1) 22-bit counter without 16-word boundary limitation and (2) 4-bit counter with 16-word boundary limitation.

    By the way, the timing between RDINH/RDOUTH and TRPLY meets the specification in the LSI-11 BUS SPEC document but violates that in the KA680 CPU module technical manual. The post-fit simulation shows the interval is about 13 ns.
    I wrote the simple HDL code, but post-fit simulation still gave 13 ns interval, being longer than 8 ns. Maybe it is the limitation of CPLD speed.
    In which way does it violate it? Which figure and which cycle are you referring to? I think as long as the order of the transitions is correct you cannot violate the Q-Bus Specs if you observe all minimal times.
    For more information about my projects see https://www.5volts.ch

  10. #10

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    Quote Originally Posted by cbscpe View Post
    In which way does it violate it? Which figure and which cycle are you referring to? I think as long as the order of the transitions is correct you cannot violate the Q-Bus Specs if you observe all minimal times.
    p. F-7 of "KA680 CPU Module Technical Manual" describes
    The slave device responds to BDIN L active as follows:
    - Asserts BRPLY L between 0 ns (minimum) and 8 ns (maximum, to avoid bus timeout) after receiving BDIN L....
    while the maximum in LSI-11 bus spec is 8 us. Also, the maximum of DATO in the KA680 manual is 10 us (p. F-12).

    If "8 ns" is a typo, it becomes easier to implement the TRPLYH signal generation.

    coredump

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