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Thread: Circuit design questions

  1. #21
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    Unless it's a matter of a shared bus (e.g. SCSI), I generally avoid wire-ORing (or, in the case of TTL, wire-NANDing), as it's slower than totem-pole outputs and can create problems. If you're wire-ORing a non-bus design to save a few gates here and there, it's not worth the trouble, unless you know that the design can tolerate slower rise and fall times and deal with any race conditions that may arise as a result.

    Back in the day of RTL and DTL, wire OR-ing was much more common.

  2. #22
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    Well, it has been working 'as is' for a long time. I suppose that I could eliminate some of them in the future. The worst case length is under 10 inches. I have pull up resistors on both ends. Maybe I could experiment with the values. Reason I have the pull up's on both ends is that I want to be able to run the machine with some of the boards out of the motherboard, mostly for troubleshooting. Thanks for the help, Mike

  3. #23
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    RTL and DTL used single-ended resistor loads on their logic gates, so wired-OR was pretty much standard practice--but DTL and RTL are much slower than TTL.. TTL/LSTTL use active pullup ("totem pole" or "push-pull" outputs). You could wire-OR 74L-series logic because of the internal 500 ohm resistor used in the output stage (I believe the Altari 8800 front panel uses at least one 74L-series IC for just this reason). You need only contrast the propagation delay of a 74L00 with a 7400 or 74LS00 to see what the cost is. If you're wire-ORing TTL, I trust that you're using substantial pullup (470 -100 ohm) to keep things behaving.

  4. #24

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    Probably in computing design the better way to mix and share signals onto one line is with tri-state buffers as you then have low impedance output stages in the buffers to pull the line both high and low with a fast rise and fall time for both, versus say some open collector transistors and resistor pullups.

    The problem then becomes more critical for timing, to avoid one buffer coupling pulses onto the line when another is also doing it, then the buffer outputs "fight" each other. I had this problem not long back where one of the lines in the SOL-20 was fighting an output from a Matrox ALT 512 graphics card. Obviously Matrox didn't know PT had used the same control line. So when I tried to recover data from the graphics RAM on the Matrox card, to load it to general memory, every now and again an error would occur when the tri-state buffer on the Sol mobo put pulses on the the particular line, it took me a long time to find this contention. I spotted it by seeing a brief anomalous logic level on the scope.

    So if tri-state buffers are used, watch out for the timing.

    If you only have a few sources of pulses to mix onto one line and only need a small number of tri-state buffer IC's some simple logic gating could be arranged so that if any one of the buffer arrays is enabled, the other are locked out, and that might give the best of both worlds and avoid any contention that way.
    Last edited by Hugo Holden; March 27th, 2020 at 05:31 PM.

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