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Thread: Z80 Hello World example in hex

  1. Default

    Quote Originally Posted by dreNorteR View Post
    edit: I meant the code jumped to by RST 38H, which isn't actually the interrupt handler. D'oh! It's using IM2 with the vector somewhere in page 0.
    And RST 38 is actually invoked from the NMI.

    The init outputs are likely for a Z80 PIO, setting the vector to 6. Here is the interrupt handler, all three instructions of it:

    Code:
    0069 IN   A,(00)        ;load input directly into A!
    006B EI                 ;bug? should be left disabled
    006C RETI

  2. #12
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    NMI on the Z80 goes to 0066H; IM 1 interrupts go to 0038H. What's interesting about RST 38H is that the hex code is 0FFH.

    I would likewise like to see photos of the unit.
    --
    Thus spake Tandy Xenix System III version 3.2: "Bughlt: Sckmud Shut her down Scotty, she's sucking mud again!"

  3. Default

    Quote Originally Posted by lowen
    NMI on the Z80 goes to 0066H; IM 1 interrupts go to 0038H. What's interesting about RST 38H is that the hex code is 0FFH.

    I would likewise like to see photos of the unit.
    Yes, the code I posted is for the regular interrupt handler. NMI does RST 38H + RETN.

    Quote Originally Posted by Eudimorphodon View Post
    Please tell me that this Homered machine looks exactly like this!

    Attachment 61003
    If Homer Simpson knew Z80 assembly, he might indeed write something like this

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    You beat me to the post about most of what I have scribbled down on my bit of paper.

    I agree that the command set appears to be 'g' and 'l' (lower case).

    The screen (I suspect) is 1K starting from 0x0C00.

    Based on that we can write Brad's "Hello World" program for him if we knew how to initially load the program...

    I have seen reference to the text for "PCSPAF...", so I am guessing this could be printed out if an executed program returns to the monitor?

    There has to be an intelligent Z80 peripheral on this board somewhere (be it an SIO or a PIO) for a serial or parallel keyboard respectively.

    The interrupts will be disabled on a RESET, so the EI just before the initial HALT is required for the SIO/PIO maskable interrupt to correctly operate.

    I suspect (with the stack being at 0x7E0) that there must be RAM from here downwards, so the ERPOM is probably 1K in size (0x0000 to 0x03FF).

    It makes me want to get my 'little' homebrew Z80 out again - Z80 CPU, PIO, SIO, SP0256 speech output, RTC, seven segment displays and some form of speech analysis chip that I never did get to work. It was a very intelligent clock with multiple alarms and speech output as well as the display. I was also working on making it respond to speech commands. Perhaps I can convert it from a clock to a 'real' micro with an operating system ?! Let me see how much EPROM and RAM I put on the machine. Knowing me a large EPROM and 8K or 32K RAM - so that could make a reasonable CPM system!

    NO! Must resist temptation and get back to work approving test specification documents ! No time for this interesting stuff...

    Dave
    Last edited by daver2; May 19th, 2020 at 04:20 AM.

  5. Default

    Quote Originally Posted by daver2 View Post
    You beat me to the post about most of what I have scribbled down on my bit of paper.

    I agree that the command set appears to be 'g' and 'l' (lower case).

    The screen (I suspect) is 1K starting from 0x0C00.

    Based on that we can write Brad's "Hello World" program for him if we knew how to initially load the program...

    I have seen reference to the text for "PCSPAF...", so I am guessing this could be printed out if an executed program returns to the monitor?
    It's the NMI handler that dumps the registers. Must have a button for that on the machine.

    I hacked a quick-and-dirty emulator and was able to input & run a simple program using it.

    The L command is actually not that bad, kind of a full screen editor except only 16 bytes, one on each line. It even has some control keys:
    ^H: byte up
    ^M: byte down (skip forward without changing memory)
    ^J: page down (16 bytes)
    ^L: page up

    CPU reset seems to be the only way to exit it.

    Code:
                     ORG 0800
    
    0800 F3          DI           ;disable intrs to keep A safe
    0801 11 00 0C    LD   DE,0C00 ;start of video RAM (512 bytes)
    
    OUTER LOOP:
    0804 21 17 08    LD   HL,0817 ;start of message
    
    CHAR LOOP:
    0807 7A          LD   A,D     ;get output page
    0808 FE 0E       CP   0E      ;compare with end
    080A 38 03       JR   C,+3    ;still on screen...
    080C FB          EI           ;enable intrs
    080D 76          HALT         ;wait for key
    080E C7          RST  00      ;back to monitor
    
    OUTPUT CHAR:
    080F 7E          LD   A,(HL)  ;get char
    0810 B7          OR   A       ;is it zero?
    0811 28 F1       JR   Z,-15   ;yes, loop back to start of msg
    0813 ED A0       LDI          ;move to video
    0815 18 F0       JR   -16     ;next char
    
    MESSAGE:
    0817 48 45 4C 4C "HELL"
    081B 4F 20 57 4F "O WO"
    081F 52 4C 44 21 "RLD!"
    0823 00
    edit:
    I kind of assumed it had at least 2K of RAM, but it might not be more than 1K if the video RAM is separate. The commands use 0400 as default address and SP being nearly at the top would make sense.

    0000-03FF 1K ROM
    0400-07FF 1K RAM
    0800-0BFF 1K ???
    0C00-0DFF 512 byte video (16 rows x 32 columns)
    Last edited by dreNorteR; May 19th, 2020 at 06:49 AM.

  6. #16

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    I thought I'd bring a little history about the 2758.
    First the creation of the first EPROM was done by Intel. It was a significant step, almost more important than the micro processor itself that was going to happen anyway. The first EPROM was the 1702 (1701,1601,1602,4702,8702 and a number of variants ). It was PMOS and used +5V and -10V(-9V). The next EPROM was the 2708. This also required a negative rail ( don't recall if it was PMOS or NMOS ). Intel followed this with the 2716. This was a NMOS part and only required +5V ( not counting programming voltages ).
    Soon TI came up with the 2508. It was the same data size as the 2708 but only needed the +5V rail. Intel had no competing part other than the two rail 2708.
    The 2716 were just coming off the line and sold for around $60 each. Intel realized that they could take their half bad 2716s and sell them as a single rail 2708. They called the part a 2758 to not get confused with the 2508 of TI. The parts sold for around $30. If you look on the label of the part these would have a Hi or LOW printed on them indicating which half was bad ( A10 setting ).
    I recall seeing a price list when 2716s were sold for around $6. The price list included the 2758. It was still $32 ea. I always wondered how many purchasing agents know that the 2716 was a drop in replacement for a 2758.
    Dwight

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    Quote Originally Posted by dreNorteR View Post
    And RST 38 is actually invoked from the NMI.

    The init outputs are likely for a Z80 PIO, setting the vector to 6. Here is the interrupt handler, all three instructions of it:

    Code:
    0069 IN   A,(00)        ;load input directly into A!
    006B EI                 ;bug? should be left disabled
    006C RETI
    Having the IRQ re-enabling EI immediately prior to RETI was standard practice; EI enables the maskable IRQ after the instruction FOLLOWING the EI; that is, after the RETI. RETI is of course used so that the PIO or SIO can sniff the opcode off the bus and reset their state, go to the next in the Z80 IM 2 chain, etc.

    EDIT: Note: While RETN does do the IFF dance to restore the IRQ mask state, RETI does NOT.

    The TRS-80 Model II is a good study in an IM 2 machine, and the rather distinctive way those Z80 peripheral chips are set up with a series of outs to a single port is a bit of a fingerprint. For the LS-DOS 6 port to the Model II the peripheral chip set data was just that, data tables, with a somewhat generic setup loop that read the data tables and stuffed the bytes out the port one by one. The Z80 DMA was set up the same way for each transfer.....
    --
    Thus spake Tandy Xenix System III version 3.2: "Bughlt: Sckmud Shut her down Scotty, she's sucking mud again!"

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    I assume when you press the 'g' key, the monitor responds with the text message "GH TO". I assume this should be "GO TO". We can now fix the bug !

    I suspect the screen size is really 1024 bytes. My assessment of the start-up code is that it clears 256+256=512 bytes out with one restart instruction ( RST 0x08 ) and then carries on to clear a further 256+256=512 bytes out with a subsequent call of a different restart instruction ( RST 0x10 ). DE will have been incremented accordingly, and B would be zero after it had been decremented to zero - so would perform the dance again..

    We could reduce the "HELLO WORLD!" program to:

    Code:
    DI
    LD HL, start of "HELLO WORLD!" string.
    LD C, number of characters in the "HELLO WORLD!" string.
    RST 0x18 ; Display string to screen.
    HLT ; Use RESET to recover.
    Dave
    Last edited by daver2; May 19th, 2020 at 08:45 AM.

  9. Default

    Quote Originally Posted by daver2 View Post
    I assume when you press the 'g' key, the monitor responds with the text message "GH TO". I assume this should be "GO TO". We can now fix the bug !
    Noticed that too. Bit rot?

    I suspect the screen size is really 1024 bytes. My assessment of the start-up code is that it clears 256+256=512 bytes out with one restart instruction (RST 0x0 and then carries on to clear a further 256+256=512 bytes out with a subsequent call of a different restart instruction (RST 0x10). DE will have been incremented accordingly, and B would be zero after it had been decremented to zero - so would perform the dance again..
    There is no second RST, it just sets up the registers and falls thru to RST 10H. The screen is clearly 16 rows by 32 chars, otherwise the output from the L command wouldn't make sense:

    Code:
    0400 00-
    0401 00
    0402 00
    0403 00
    0404 00
    0405 00
    0406 00
    0407 00
    0408 00
    0409 00
    040A 00
    040B 00
    040C 00
    040D 00
    040E 00
    040F 00
    The dash to the right on the first line is the "cursor". If you type a hex digit (or really any non-control key, there's no error checking), it shifts whatever byte is in memory at that location left and adds what you typed, automatically moving down with every second digit. After 16 lines it wraps around to the top. There are also keys to go up or down by 16 line pages.

    Re: IRQs, enabling them before RETI may be standard, but whatever is in the A register will be overwritten when you press a key. So interrupts should really only be enabled when the program is halted waiting for a key, and turned off again until it is ready for the next one.
    Last edited by dreNorteR; May 19th, 2020 at 08:57 AM.

  10. #20
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    The initialisation code at address 0x0088 invokes RST 0x08 which initialises registers DE, B and A and then falls through to the code that is within RST 0x10 to actually clear 256+256=512 bytes pointed to by DE.

    The return causes the RST 0x10 to be invoked again at address 0x0089.

    This causes DE, B and A to continue where they left off from and should clear a further 256+256=512 bytes before returning again to the main initialisation code.

    Whether this is intentional (as there is 1K of VDU memory) or whether only 512 bytes are actually displayed out of the 1K I do not know.

    I agree with the interrupts though - that has been bothering me...

    Dave

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