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Thread: TTL 74181 ALU, Need an ACCUMULATOR Register, Suggestions?

  1. #1
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    Default TTL 74181 ALU, Need an ACCUMULATOR Register, Suggestions?

    Hi, I am building a simple computer for fun that uses the 74181 Arithmetic Logic Units. These ALUs were the basis of some of the older vintage computer designs. I am trying to identify a Register part number to use for the Accumulator (ACC). A unique feature of the ACC is that it stores the ALU combinatorial result, but does not change output state until the negative clock transition. (The ALU result depends on the input from the registers.) I can find all sorts of registers that change output on the positive clock transition, but not on the negative. Am I missing something? If I can't find a register with this property, I will have to store the ALU result in a temporary location, and load it back to the register for the ALU to use. Thanks! Michael

  2. #2

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    You can use whatever register I guess. 74175 is four bits. DEC often use 7489 for the register file. 16 registers in one chip. Another option is the 74170/74670 which has separate read and write ports. Only four registers though. Whatever edge is used for storing can be handled by an external inverter. Positive edge is the most common.

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    You could always invert the clock signal...

    Checkout the PDP-8 LD12 - this is an existing design for exactly what you are trying to do!

    Dave

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    You might want to look through the old UK ACC magazines here :-

    http://www.smrcc.org.uk/members/g4ugm/acc.htm

    there is a design for a TTL computer using 74181 ALU's in there, although there are many others on the net.
    Dave
    G4UGM

    Looking for Analog Computers, Drum Plotters, and Graphics Terminals

  5. #5

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    if this is a design you are doing (not an existing design) you should consider latching all registers and state changes on the positive clock edge.
    Most of the synchronous logic components are pos. edge. You don't want inverters or gates in the clock path. (race condition)
    Your registers should be edge triggered not transparent. The output will change after the clock but the input will already be latched.
    The register then will contain the values before the clock edge.
    This is what input hold and propagation delay are all about.

  6. #6

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    You don't want to store the data on the same edge as it changes you really want to wait a half cycle to let propagate and capture on the positive edge. You don't want to try to capture it on the same edge that it changes unless you use a delayed clock.
    Think of it as like a bucket fire line. Data is passed on one half cycle and grabbed on the other other. Nothing works well if every one is grabbing at the same time. Half need to pass at the same time the other half is passing.
    Dwight

  7. #7

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    I wonder how every FPGA manufacturer got this so wrong. They all do common single phase clock with edge triggered latches.

    Please Google synchronous logic

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    Quote Originally Posted by jlang View Post
    I wonder how every FPGA manufacturer got this so wrong. They all do common single phase clock with edge triggered latches.

    Please Google synchronous logic
    What makes you think that? When I built the Baby Baby (Really SSEM)

    https://hackaday.com/2016/01/06/baby...er-on-an-fpga/

    I have multiple phase clocks and clock things on multiple clock edges. Of course this slows you down because you have to divide the master clock, but for many problems its fast enough so you don't care.
    Dave
    G4UGM

    Looking for Analog Computers, Drum Plotters, and Graphics Terminals

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    My recollection is that for the 74xxx systems, it was not uncommon to see a 74199 or 198 used as an ALU register. You get shifting capabilities out of it as well, which can be handy in an ALU. These ICs were not included in the move to LS logic and are 24-pin wide packages, so they're strictly period-correct.

  10. #10

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    If the logic was created with latches, they would have pos-edge and neg-edge clocked latches. You can not make functional logic with latches of all the same phase, unless you have no feedback. Sometimes, one can design multiple latches of the same phase clock in series but in these, they still need at least one of the opposite phase before there is feedback. This same phase latch is used to hold a value longer that might have a lot of logic. In these cases, there is a delayed clock. I doubt this type of design is ever used as the programmable part of a FPGA but may be used in RAM blocks within a FPGA.
    Using edge clocked flops, it can be done. In a FPGA, the compiler you use, should understand the terms setup and hold time limitations.
    When flops are made, even inside TTL ICs, they are usually made with two latches. The clocks are controlled so that on the specified D to Q, the input latch is guaranteed to be opaque when the output latch is made transparent. This is done by slightly distorting the threshold of the clocks into the latches. In CMOS designs for high speed computing, it is not uncommon to see both latch transparent when the clock goes high ( for pos-edge flop ). This type of design requires a minimum delay between flops. It makes for faster logic but requires more careful design.
    When designing logic, one has to be careful to understand setup time and hold time limitations. For TTL, with just buffers, one has enough delay to use the same edge clocks with flops. One can do latch design as well but again, you still need to understand setup and hold times.
    It is possible to make the same phase latch designs but that requires minimum delay and a very short clock pulse, not a typical symmetric 50/50 duty cycle clock.
    Dwight

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