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Thread: How does a DOS SYS driver enable a file system / drive?

  1. #41
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    I note that the DDJ code also includes parallel-port connections (nibble at a time), so that should be useful.

  2. #42

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    I received a DB25 breakout today so I got to do to some port toggling to see how fast it can go.

    Despite the system I'm using being a P3-700 MHz, apparently the bus the parallel port is on is 8 Mhz or so limiting the maximum toggle speed to 1 MHz or so.

    Here is my question - when an OUT instruction is executed on a "fast" 700 MHz CPU, does everything come to a crawling halt while it waits to use the slow ISA bus?

    In this case, does it really matter so much how optimized the instructions are if the OUT instruction ends up being a huge bottleneck anyway? For slower CPU's it would be more relevant?

    Even pulling a byte from a buffer, putting it on D0-D7, then toggling strobe low/high I was able to get over 350KB/s. That is not with it waiting on an ACK signal though and I'm sure that will slow it down quite a bit.

  3. #43
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    Yes, the ISA bus is what it is.

  4. #44

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    Here is my plan so far. I'm going to setup an atmega1284 (18.432 MHz) on a breadboard so it can provide the handshaking response and start testing it. FATFS will be able to talk SPI with the micro SD at 9.216 MHz (clk/2).

    I need a packet based transaction between the PC and AVR over the parallel port, so I need framing, crc error detection, re-transmit, etc. I'm going to support 4 parallel port types (SPP, PS2, EPP, ECP), but essentially only SPP, PS2, and EPP modes since ECP can emulate any of them. ECP is going to be put into EPP/PS2/SPP mode, but I don't plan on having an ECP mode. I don't plan on supporting any IEEE1284 negotiation for the mode. The driver on the PC will detect the port type and use the fastest one unless there is a command line override.

    SPP mode is 8 bits transmit, 4 bit receive (two nibbles to make a byte)
    PS2 mode is 8 bits transmit, 8 bits receive
    EPP mode is 8 bits transmit, 8 bits receive, parallel hardware handles handshaking

    The signals for EPP mode will work for PS2 mode as well, I just have to do them manually instead of the hardware doing them. One alteration is that instead of 5 port accesses (set data, raise strobe, wait for remote strobe, lower strobe, wait for remote strobe de-assert), I am going to try 3 port accesses instead (set data, toggle strobe, wait for remote strobe toggle).

    I'm going to support:
    SPP detection, SPP mode

    PS2 detection, PS2 mode
    PS2 detection, SPP mode /spp override

    EPP detection, EPP mode
    EPP detection, PS2 mode /ps2 override
    EPP detection, SPP mode /spp override

    ECP detection, EPP mode
    ECP detection, PS2 mode /ps2 override
    ECP detection, SPP mode /spp override

    I'm attaching a PNG that shows the signals for each port. C2 (nInit) is available in EPP so I plan to use it as a packet frame signal. I will take it to to signify the beginning of a packet and then return it high when the packet it finished. Like EPP I will use C0 (nWrite) to indicate whether the packet is a read or a write. I will use the status bits to indicate some things as well. S3 indicates that the AVR side has a packet ready for reading if the PC wants to read it. S4 indicates that the AVR is not busy and ready to communicate. S5 indicates that the last packet sent by the PC failed crc.

    EPP timings are very tight and that may be the toughest thing to contend with. The 10us timeouts aren't too bad, but the 125ns timeout is near impossible although parallel port complete suggested that it wasn't the end of the world if it went a bit longer.

    Obviously during a read transaction using SPP the S3/S4/S5 will be used to send nibbles.

    signals.png

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