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Thread: Original-IBM-5150 or IBM-Clone Memory Experimentation Thread

  1. #21
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    ... per the above, it just occurred to me how you could decode 640k with mixed 256k and 64k DRAMs using the same one Ď139.

    • On the first decoder use the outputs corresponding with 0-256k and 256k-512k directly to enable the two 256k banks.
    • Use the output for 512k-768k as enable for the second decoder.
    • Use the lines that correspond to 512k-576k and 576k-640k as enables for the two 64k banks.


    Not saying Sanyo did that, but itís a method that could be achieved with just a few jumpers.
    My Retro-computing YouTube Channel (updates... eventually?): Paleozoic PCs

  2. #22
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    I do see quite a few 138 chips. Also, I see jumpers on the board that are either unpopulated or unshorted.

    I'll figure it out when I refurbish the board mask.

  3. #23
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    Good news! I've completed the mask repair (The ultraviolet flashlight worked perfectly!) and inserted the memory sockets.

    Not so good news, I don't have a display yet, because the memory (512kb at the moment) won't work. (I still have to look at the 5160 schematics to redirect the proper signals.) But for now, my mind is fried, and I can't retain the schematic tracings mentally yet.

  4. #24
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    (This will expand as I look at the schematics)

    Ok, on the memory banks, Pin 1 of all the memory chips ( Address Line 8 ) goes to a resistor that is marked "30". (It's on PDF Page 74 / Book Page 1-52 of the 5160 Technical Reference) I'm a bit confused because I don't know if that means just ohms or kilo-ohms.

    EDIT: Never Mind, the resistor is indeed 30 ohms. (I measured it with a multimeter)

    Update: It does indeed seem that Sanyo had intended to make the MBC-775 or (maybe) similar models expandable to 640k. Address Line 8 is attached to the 30 ohm resistor, which is tied to pin 4 of the additional LS158 chip, just like on the 5160 schematic. I'll check the rest of the circuit upwind from that, then see where the buffer delay line needs to go. (I detached that because the factory patch wire leading from the buffer delay line to the LS158 seems to be in a different place on the schematic, and I needed to detach it to clean the final through-hole and insert the chip socket for the LS158.)

    Update 2: Ok, the 158-to-buffer-delay-line wire should stay where it was. (It's ok, I've been taking pictures before I change anything, to prevent problems in reversing small mistakes)

    On the other hand, it's odd, because the delay line IC in my Sanyo does not match the schematic exactly. It's actually supposed to be on Pin 3 (IBM) instead of Pin 4 (Sanyo), but the pin for that delay (60ns) is not present:

    IBM's Pins (TTLDL-20):
    12: 20ns
    4: 40ns
    3: 60ns
    6: 80ns
    5: 100ns

    Sanyo's Pins ( 201JHT1006L, assuming equal divisions, because the datasheet does not have delay markings, and this was the only datasheet I could find!):
    11: 25ns
    4: 50ns
    10: 75ns
    5: 100ns

    EDIT: I'm also assuming that the memory bank CLOSEST to the CPU is bank 0? (I'm checking if I have the memory ICs in the correct sockets.)
    Last edited by T-Squared; October 29th, 2020 at 10:44 AM.

  5. #25
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    RN3 is 30R = 30 Ohms.

    Looked in my 5160 at Rn3
    IBM_5160_RN3-Weerstand-Waarde30.jpg

  6. #26
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    Ok, I've run into a small problem. The A/B inputs of the extra 158 are not connected to any of the Y outputs of any 244 chip.

    According to the schematic, they should be tied to a 244 chip that is grounded. I don't know what ICs they are on my Sanyo yet, but it's easy to figure out. On the IBM, though, they are U14 and U16

    EDIT: Ok, it seems they are all grounded on the Sanyo.
    Last edited by T-Squared; October 29th, 2020 at 12:10 PM.

  7. #27
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    Quote Originally Posted by Eudimorphodon View Post
    ... per the above, it just occurred to me how you could decode 640k with mixed 256k and 64k DRAMs using the same one ‘139.
    You were talking about this? Guess what I happened to find over near the buffer delay line IC? A footprint for an LS139. That may be what I need.

  8. #28
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    Right now, and for the past day or so, I've been mapping out the connections between the LS158s and the LS244s. (based on the schematics in the 5160 Technical Reference)

    Some of the pins on the 158s don't go anywhere. I'm wondering if I can use a free LS244 input-pair to tie the memory in properly...

  9. #29
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    At first glance, the memory decoding seems to be controlled by four 224 chips, and two 373 chips. (Along with the 158s and 138s)

    (Again, this is at first glance. I'm not saying that there are more yet.)

  10. #30
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    Ok, there's three 158 chips, two 138s, four 244s (yeah, I called them 224s by accident), THREE 373s, and three 245s.

    The thing with this setup is, the way they are wired does not match the schematics of the 5160. Probing the pins of the chips and checking continuity doesn't show the same pathways as the schematics. (I can post my findings later, if you want.)

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