Image Map Image Map
Page 3 of 3 FirstFirst 123
Results 21 to 26 of 26

Thread: Netronics Explorer 85

  1. #21
    Join Date
    Jan 2011
    Location
    Vancouver, BC
    Posts
    5,057
    Blog Entries
    3

    Default

    No worries. I think we have something custom going on here.. I'm poring over schematics and comparing to these jumper wires he has around. I note the machine usually powers up in a ready state, rather than requiring the reset button to be ready for the terminal space-bar go ahead. I wonder if they set it up that way on purpose.

  2. #22
    Join Date
    Jun 2012
    Location
    UK - Worcester
    Posts
    4,091

    Default

    It has a very rudimentary power-on reset (POR) circuit consisting of C106 (0.1uF) and R113 (3k9). This is very, very basic and (as implemented) may work - but it may not... This is why more reliable POR circuits were developed - and then ICs incorporating the circuitry. It looks like you are fortunate in that the POR circuit works! Netronics have covered themselves in the documentation by stating that you have to operate the RESET switch/button...

    Dave

  3. #23
    Join Date
    Jun 2012
    Location
    UK - Worcester
    Posts
    4,091

    Default

    There is some 'horrible' circuit surgery gone on underneath with the snipped yellow wire and the short blue wire on the bottom of U202 (the missing 74LS20).

    It looks like the snipped yellow wire went from U106 pin 7 (IO/nM) to U203 pin 3 (GND)? This will never work (possibly the reason why it is cut!!!).

    Equally bad it looks like the little blue wire goes from U202 pin 14 (VCC) to U202 pins 4 and 5. Nooooo!

    Not sure what someone was trying to do here?

    It looks like someone has managed to get a working Level A and then added the additional S100 buffers, RAM and ROM - and screwed up the modification.

    If you can make a detailed analysis of the link positions and where the bits of wire go from to (ICs and pin numbers or pad letters) and then post back please.

    Cheers,

    Dave

  4. #24
    Join Date
    Jan 2011
    Location
    Vancouver, BC
    Posts
    5,057
    Blog Entries
    3

    Default

    Ok so we have a wire going from J2 pin 22 (? there aren't 24 pins but 24 is right next to the last pin in the line) to pin 33 of U105
    We have a wire from S17 to pin 25 of U105 also.
    We have a wire from X to W
    We have a wire from pin 14 of U202 that connects to both pins 4 and 5 of U202
    We have a wire from pin 9 of U115 to pin 5 of U215
    We have a cut wire from pin 3 of U203 to pin 7 of u106

  5. #25
    Join Date
    Jan 2011
    Location
    Vancouver, BC
    Posts
    5,057
    Blog Entries
    3

    Default

    Also it looks like there was some repair work done with the innermost S100 slot.. he's got jumper wires there that appear to connect the same points as the tracks did. I don't see evidence these were cut but who knows.

  6. #26
    Join Date
    Jun 2012
    Location
    UK - Worcester
    Posts
    4,091

    Default

    Thanks for your 'bits of wire' information.

    Some of these are correct to the documentation, some are correct to the documentation - but not to exactly the same pins as the documentation and some are just darn right wrong...

    The U202/14 to U202/4 and U202/5 is a complete bodge - but I wouldn't remove it just yet until we find what is wrong.

    The U203/3 to U106/7 is also a complete bodge. This is the cut yellow wire isn't it? if so, do not connect this wire at all - it will make the machine malfunction.

    Not quite sure about S17 yet. Is S17 in or out? EDIT: This link configures the line length. I can't see whether the link is IN or OUT from your photograph however.

    J2/22 to U105/33 (PB1) looks wrong. According to the documentation J2/22 should be connected to U105/28 (PA4). Again, I wouldn't change this just yet.

    I am trying to work out why the debug monitor is appearing where it shouldn't - and think I may have stumbled on the reason...

    As the 8085 resets to $0000 (RAM) - but the debug monitor starts at $F000 - some special logic needs to be present for this to work. What I think happens is that on a reset the debug monitor is enabled and 'shadows' itself over memory. I haven't quite worked out the logic yet, but I would like you to take a couple of measurements if you wouldn't mind.

    U107/11 is incorrectly identified as /MONITOR CS. This signal is connected to U105 pin 2 - which is an active HIGH chip select - hence it should be labelled "MONITOR CS".

    When you have powered up the machine (and pressed the local reset switch) can you look at the logic level on U107 pin 12 (/BOOT ACTIVE). I would like to bet it is LOW ('0') permanently. This would permanently enable the monitor ROM irrespective of the setting of switches SW200 and SW201.

    If this is the case, we will need to find out how the DEBUG MONITOR disables this latch formed from U108/6 and U115/12.

    EDIT: I can also see how the /BOOT ACTIVE signal (from U115/12) will prevent the BASIC ROM from being read.

    Dave
    Last edited by daver2; October 31st, 2020 at 12:05 PM.

Bookmarks

Posting Permissions

  • You may not post new threads
  • You may not post replies
  • You may not post attachments
  • You may not edit your posts
  •