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Thread: CBM 8032 - What does the startup chirp actually mean?

  1. #61
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    My idea was a ‘NOP generator for the data bus’...

    Hence the reason I didn’t write to the registers of the CRTC itself. Plus, I didn’t want to write ‘random’ data to it. Logic would be to have the monitor disconnected whilst trying this test, but if someone doesn’t - the code will not do any damage.

    Yes about my jump! That’s the problem with “knocking something up without a written Spec. or testing it”!

    The other option is replacing the LDA #0 with a couple of NOPs ($EA) or omitting them altogether and saving two bytes. It doesn’t technically matter what value we start at. In fact, register ‘A’ will have a value determined by the initialisation instructions within the Kernal ROM before calling the EDIT ROMs initialisation entry point at $E000.

    Thanks for the feedback as usual Dave.

    Dave

  2. #62
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    Quote Originally Posted by daver2 View Post
    My idea was a ‘NOP generator for the data bus’...
    Dave,
    Excellent idea of Data Bus NOP Generator! It is a much needed tool.

    I'll cut an EPROM and ship to Mike. In the mean time, would it make sense to have him build a simple NOP Generator to check out the Address Bus?

    -Other Dave

    EDIT: Why did you say for BASIC 4 only? This should work on any PET...
    Last edited by dave_m; November 27th, 2020 at 10:29 AM.

  3. #63
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    >>> would it make sense to have him build a simple NOP Generator to check out the Address Bus?

    I think it would. I can conceive of an addressing fault whereby the instructions are executed to initialise the CRTC and make the chirp, but the data table that is being utilised to program the CRTC ends up pointing at the wrong place. Small probability of course - but not 0.

    The PET ROMs use page 0 RAM as an indirect pointer to the CRTC initialisation data table, but I don't within my PETTESTER ROM. My table is at a different address to the PET ROMs - so getting less and less likely I think.

    After all, a NOP generator is only a couple of IC sockets and a few resistors - and very useful to have. I would like to bet we may even need it next...

    Dave
    Last edited by daver2; November 27th, 2020 at 10:36 AM.

  4. #64
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    Quote Originally Posted by daver2 View Post

    I would like to bet we may even need it next...
    Pessimist!

  5. #65
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    Or realist ?!

    Dave

  6. #66
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    Default Display Enable from 6545

    I've been reviewing the 6545 CRTC spec sheet (similar to 6845), and we can look at an output of the CRTC called Display Enable (UB13-pin18 ).


    If the CRTC was initialized correctly, we should see a pulse train with a period of 64 uS except during the Vertical Blanking (at a 60 Hz rate) when it should be Low for at least 4 mS every 16.66 mS.


    If we see this, the CRTC was initialized correctly and the problem is with the CRTC Vertical Drive output or something on the output the Vertical Drive (UB13-pin 40).


    If the pulse train does not have this period of Low every 16.66 mS then it was not initialized correctly (due to fault on Data Bus), or there is a problem with the 6845 input register. We can use the new test EPROM to help us determine if there is a fault on the Data Bus.


    If this holds logic, let's have Mike capture the trace on UB13-pin18 while the PETTEST version 4 EPROM is in place. He can also find the signal at UB1-pin2.


    Here is a scope photo of Vertical Sync to the monitor on top trace, and Display Enable on the bottom. The Time Base setting is 2 mS per division.
    -dave_m

    6545 Display enable.jpg
    Last edited by dave_m; November 27th, 2020 at 03:45 PM. Reason: typos

  7. #67
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    Hi Dave_M and Daver,

    Firstly, sorry, I do not have any logic analyzer equipment.
    I have received the vintage 6502 that I ordered (It is a Rockwell chip from 1990) so, I put this into the board along with a second 6845 (just on the off chance that the first 6845 was bad). These made no difference, so, I think it is fairly safe to assume that the 6502 and the 6845 are good chips.

    There is a lot of information in your previous few posts, I'm not sure how much of I fully understand What would be the best next step - Have a crack at building a NOP Generator or put the scope on UB13-Pin18?

    Thanks Guys!!
    Mike

  8. #68
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    Quote Originally Posted by MikeP View Post
    What would be the best next step - Have a crack at building a NOP Generator or put the scope on UB13-Pin18?
    Try the scope measurement first. Display Enable can be found at UB1-pin2, an easy place to to probe on the front edge of the board. Use a negative trigger and a 2 mS per division timebase.

    Then we will show you how to make a NOP Generator out of a couple of 40 pin sockets and a pull-up resistor if you can find a resistor between 1K and 100K, otherwise we can do without it. One of the dave's will find the wiring diagram for the sockets. The wires will force $EA [1110 1010] on the CPU data bus. $EA is a No Operation instruction that will cause the CPU to 'do nothing' and go on to fetch the next NOP instruction happily incrementing the address lines forever. You can then take your time in scoping the address lines looking for the proper square waves frequencies.

    Your problem is starting to look like something is causing a fault on the address bus or the data bus. The NOP Generator will test the address lines and the new EPROM I will send you will test the data lines.

  9. #69
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    Hi Dave_M,

    I followed your instructions and there is no signal on UB1-Pin2 (or UB13-Pin18 ). Attached is the scope output.UB1-Pin2.png

    Regarding the NOP Generator, I do have 40 pin sockets (the round pin type) and I have an assortment of resistors.
    Thanks
    Mike
    Last edited by MikeP; November 29th, 2020 at 11:07 PM. Reason: Typo

  10. #70
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    Thanks Mike,

    I have been re-reading the latest posts again, and I am still seeing a few inconsistencies.

    For example, UB13 pin 18 (DISP ENA) has no signal on it, but this signal percolates through three flip-flops and becomes a video enable signal at UD4 pin 13.

    Assuming this signal from the CRTC is logic 0, then this should disable the video signal to the monitor. Yet you have stated previously that you see a video signal at the connector to the monitor...

    Can I ask you to go back to the monitor connector and remeasure the H DRIVE, V DRIVE and VIDEO signals again please? Sorry to be a pain, but consistency is important - otherwise we can end up down blind alleys.

    Dave

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